Chair: Christian Haubelt, University of Rostock, DE, Contact

Co-Chair: Dominique Borrione, TIMA Labs, FR, Contact

Topic Members (click to open)

Modeling and specification methodologies for complex, HW-SW embedded systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

Chair: jamadtu [dot] dk, Contact

Co-Chair: Luciano Lavagno, Politecnico di Torino, IT, Contact

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Synthesis of complete systems, application- and domain-specific synthesis techniques; system-level models for design, optimization and synthesis; hardware/software co-design and partitioning issues; hardware/software interface and communication synthesis; interface-based and correct-by construction designs; system-level scheduling techniques; protocol synthesis and optimization; system optimization for all cost functions (timing, electrical, non-functional); multi-objective, classical and nature-inspired optimization techniques for system level design; large-scale and industrial case studies involving full system optimization and synthesis.

Chair: Franco Fummi, Universita' di Verona, IT, Contact

Co-Chair: Mark Zwolinski, University of Southampton, UK, Contact

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Simulation-based verification; post-silicon validation; hardware/software co-simulation and validation, ATPG for validation; transaction-level validation; semi-formal verification techniques; test bench generation; design error debug and diagnosis; advanced simulation and emulation techniques from system to circuit level; simulation accelerators; multi-domain simulation techniques for mixed systems.

Chair: Tudor Murgan, Intel, DE, Contact

Co-Chair: Domenik Helms, OFFIS, DE, Contact

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Design methods, techniques and case studies of low power systems, covering aspects from specification, mapping, new algorithms, system architecture to circuit; including power minimization techniques for analog and digital circuits, HW and SW aspects, power management, batteries, energy harvesting, thermal aware computation and technology aware design aspects in nanometer technologies (i.e., leakage, variability, reliability, 3D stacking, etc);

Chair: Massimo Poncino, Politecnico di Torino, IT, Contact

Co-Chair: Jian-Jia Chen, KIT, DE, Contact

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Algorithms, techniques and tools for power and temperature modeling, estimation and optimization of electronic systems applicable at all levels of the design hierarchy, from system-level specification to layout, including software and run-time management.

Chair: Sanjukta Bhanja, University of South Florida, US, Contact

Co-Chair: Siddharth Garg, University of Waterloo, CA, Contact

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System design methods, models of computation, and case studies for emerging applications: ambient intelligence, ubiquitous computing, wearable computing, bio-inspired computation; Design automation flows and case studies for upcoming and future technologies: MEMS, BIOMEMS, Lab-on-a-chip, 3D integration, nanoscale and molecular scale circuits and systems.

Chair: Gianpiero Cabodi, Politecnico di Torino, IT, Contact

Co-Chair: Jason Baumgartner, IBM Corporation, US, Contact

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Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem-proving, abstraction and decomposition techniques, and real-time verification); technologies supporting formal verification (including SMT, SAT, BDD, ATPG, and related work); semi-formal verification techniques; applications and case studies; formal verification of IPs, SoCs, cores, real-time and embedded systems; verification in practice, namely the integration of verification into the design flow; challenges of multi-cores, both as verification targets and as verification host platforms.

Chair: Federico Angiolini, iNoCs, CH, Contact

Co-Chair: Fabien Clermidy, CEA-LETI, FR, Contact

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Architecture, modeling and design techniques for Networks-on-Chips; design methods for the on-chip interconnection network: topology, switching, routing and flow control methods; architecture and design for fault-tolerance, reliability enhancement, quality of service, dynamic voltage and frequency scaling; techniques and methodologies for NoC testing; GALS synchronization architectures for NoCs; physical design techniques and methodologies; integration of external interfaces/memory controllers with NoCs; cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; programming models for NoC-based platforms; industrial applications of NoCs; design of NoCs based on alternative technologies such as photonics/optics, wireless, 3D stacking.

Chair: Laura Pozzi, University of Lugano, CH, Contact

Co-Chair: Tulika Mitra, National University of Singapore, SG, Contact

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Architectural and micro-architectural design techniques, memory systems, power and energy efficient architectures, multi/many-core architectures, multithreading techniques and support for parallelism, modeling and performance analysis, advanced computer architecture for application-specific applications, special purpose processors and accelerators, future and emerging architectures.

Topic Members (click to open)

Synthesis of hardware systems from high-level descriptions; hardware-centric system-level synthesis, analysis, and optimization; high-level language hardware description, parsing and compilation; scheduling, allocation, and binding of operations, variables, and transfers; automatic design and optimization of data-paths, dedicated memory and communication structures, and controllers; performance, cost, and power driven architectural-level optimizations; application-specific processor generation, automatic processor customization, and accelerator synthesis.

Chair: Fadi Kurdahi, University of California at Irvine, US, Contact

Co-Chair: Marco Platzner, University of Paderborn, DE, Contact

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Statically and dynamically reconfigurable and reprogrammable systems and components: platforms and architectures, FPGAs, reconfigurable processors, design methods and tools for reconfigurable computing and communication, applications.

Chair: Jordi Cortadella, Universitat Politecnica de Catalunya, ES, Contact

Co-Chair: José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact

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Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design, statistical timing analysis, timing closure; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; PLD and FPGA synthesis; arithmetic circuits.

Chair: Ralph Otten, TU Eindhoven, NL, Contact

Co-Chair: Azadeh Davoodi, University of Wisconsin - Madison, US, Contact

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Floorplanning; automatic place and route; module generation; design rule checking and layout characterization; electrical verification; problems in deep sub-micron and high-speed design; interconnect-driven and performance-driven layout; process technology developments; design for manufacturability.

Chair: Catherine Dehollain, EPFL, CH, Contact

Co-Chair: Günhan Dündar, Boğaziçi University, TR, Contact

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CAD for analogue and mixed-signal circuits and systems: Layout, Topology generation, Architecture and System Synthesis, Modeling of AMS circuits and systems, Modeling strategies, Modeling of complex analogue mixed-signal systems, Model generation, Formal and Symbolic Techniques; Languages for AMS circuits and systems: VHDL-AMS, Verilog-AMS, SystemC-AMS, Matlab/Simulink, Ptolomy; Innovative circuit topologies and architectures: Topologies/architectures that increase robustness, Topologies/architectures that increase re-usability; Modeling and Synthesis of Multi-Domain systems: MEMS, Energy Harvesting Systems.

Chair: Stefano Grivet-Talocia, Politecnico di Torino, IT, Contact

Co-Chair: Joungho Kim, KAIST, KR, Contact

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Modeling, characterization and analysis of on and off chip interconnects, and packaging; modeling, design, and characterization of Through Silicon Vias (TSV), 3D Interconnects, and interposer; wireless interconnects via capacitive/inductive coupling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate; EMC issues in interconnects: electromagnetic emission, susceptibility and compatibility; chip-package co-design, modeling, and noise coupling issues in 3D IC and packages; high-speed channel and equalizer modeling, design, and measurement; macro-modeling, behavioral, and reduced order modeling.

Chair: Tajana Simunic Rosing, UCSD, US, Contact

Co-Chair: AYSE COSKUN, Boston University, US, Contact

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Practical design experiences in industrial projects or academic projects with high industrial relevance targeting high performance, parallel, or information technology systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, data centers, and cyber-physical systems. Topics of interest include, but are not limited to: new software architectures for parallel systems, cloud computing approaches, energy-efficient memory architectures, low-power multi-core architectures and management techniques, new communication/interconnect architectures, novel energy-efficient system designs, energy efficient programming techniques, or adaptive / learning-based methods for improving energy efficiency.

Chair: Frank Kienle, Technical University of Kaiserslautern, DE, Contact

Co-Chair: Theocharis Theocharides, University of Cyprus, CY, Contact

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Practical design experience for communication, multimedia and consumer systems like smartphones, smart-books/tablets; examples are digital integrated circuits design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software defined radio systems; embedded systems design in the field of audio, video and vision domain; Application Specific Processors (ASP)/ Digital Signal Processors (DSP) for these domains.

Chair: Davide Brunelli, University of Trento, IT, Contact

Co-Chair: Bart Vermeulen, NXP Semiconductors, NL, Contact

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Practical design experiences for transportation and energy generation and distribution systems and applications: analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures and integrated sensors and transducers, RF architectures, networks of systems, energy scavenging and harvesting methods from environmental sources. Practical applications of design methods to transportation and energy systems, including models, methods and tools, design of hardware and software components, architecture analysis and optimization, component-oriented design and system-level analysis and validation. Hardware and software solutions to address energy management: components of different nature with focus on energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems and optimization of system energy efficiency.

Chair: , Contact

Co-Chair: Martino Ruggiero, University of Bologna, IT, Contact

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Medical, healthcare, and life science applications require increasingly smarter and smaller devices and personalized medicine will lead to a significant increase in both complex lab solutions as well as a myriad of consumer-like disposable devices. Application examples such as multi-physics nano-bio transducers, cellular interfacing chips, multi-parameter biosensors, pharmaceutical assay chips, implantable and wearable wireless devices for patient monitoring and therapy will reveal complex heterogeneous microsystem designs and design methods, multi-level modeling approaches, co-development of design and process technology.

Chair: Patrick Schaumont, Virginia Tech, US, Contact

Co-Chair: Guido Bertoni, STMicroelectronics, IT, Contact

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Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

Chair: jayalaucm [dot] es, Contact

Co-Chair: Marco D. Santambrogio, Politecnico di Milano, IT, Contact

Topic Members (click to open)

This topic covers the area of reliable and adaptive systems for practical applications. The scope of this topic includes, but not limited to, the development, optimization and practical application mechanisms to compensate for aging and temperature, development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

Chair: Ahmed Jerraya, CEA Leti, FR, Contact

Co-Chair: Roberto Zafalon, STMicroelectronics, IT, Contact

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Short or brief papers with a limit of two pages are solicited that relate to industrial research and practice: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanism. Product presentations and announcements are strongly discouraged and will not be considered for publication.

Chair: Bram Kruseman, NXP Semiconductors, NL, Contact

Co-Chair: Jaume Segura, Universitat de les Illes Balears, ES, Contact

Topic Members (click to open)

Identification, characterization and modeling of defects, faults and degradation mechanisms; defect-based fault analysis, simulation and ATPG of defect-based faults; reliability analysis and modeling techniques, FMEA and physics of failure; test for noise and uncertainty; design-for-reliability and design-for-variability and their impact on test; test and reliability of redundant systems; test and reliability issues in the presence of leakage; challenges of ultra low-power design on test and reliability; modeling and test techniques for physical sources of errors such as process, voltage and temperature variations; error-resilient nano-design systems.

Chair: Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact

Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

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Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs.

Chair: Abhijit Chatterjee, Georgia Tech, US, Contact

Co-Chair: haralampos [dot] stratigopouloslip6 [dot] fr, Contact

Topic Members (click to open)

Test techniques for mixed-signal, RF and multi-GHz electronics; test techniques for embedded MEMS/bioMEMS/MOEMS sensors and actuators; assembly engineering for SiP/SoC/SoP/PoP; Failure modeling and analysis techniques; defect characterization and fault modeling; fault simulation and test generation algorithms; DfT/DfM/DfY/DfR (DfX) techniques; BIST; test coverage metrics and statistical modeling; effective defect screening techniques; diagnosis and self-repair.

Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

Co-Chair: Rohit Kapur, Synopsys, US, Contact

Topic Members (click to open)

Design-for-test, -debug, and -manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DfT techniques, DfT for secure systems, DfT economics. Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; testing 3D (TSV-based) chips; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor based test; infrastructure IP; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies.

Chair: Cecilia Metra, University of Bologna, IT, Contact

Co-Chair: Lorena Anghel, TIMA, FR, Contact

Topic Members (click to open)

Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependability evaluation, dependable system design; redundant systems design; hardware/software recovery; self-repair; fault tolerance; on-line testing and fault tolerance for industrial applications.

Chair: Giuseppe Lipari, ENS-Cachan, FR, Contact

Co-Chair: Stefan M. Petters, CISTER-ISEP, IPP, PT, Contact

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Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; tools and design methods for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications;

Chair: Bjoern Franke, University of Edinburgh, UK, Contact

Co-Chair: Heiko Falk, Ulm University, DE, Contact

Topic Members (click to open)

Software synthesis; compilers; code generation; dynamic compilation for embedded systems; software generation tool chain; software environment and generation for design space exploration (compilers, simulators, synthesis tools); retargetable compilers for MPSOC and reconfigurable platforms; compilers for embedded multi-core systems; compiler and software synthesis for low power

Chair: Wang Yi, Uppsala University, SE, Contact

Co-Chair: Saddek Bensalem, Université Joseph Fourier, FR, Contact

Topic Members (click to open)

Model-based methods for embedded system design; verification of embedded systems; model-based software architectures; model-based design for control applications; model-based software testing, software/system integration and deployment; tools for model-based embedded system design; software verification;

Chair: Gabriela Nicolescu, Ecole Polytechnique de Montreal, CA, Contact

Co-Chair: Oliver Bringmann, FZI / University of Tuebingen, DE, Contact

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Software architectures for MPSoC, multi/many-core and GPU-based systems; programming languages for embedded MPSoC, multi/many-core and GPU-based systems; virtualization for embedded systems, including safety and security aspects; resources constrained middleware and Run-Time Environment (RTE) architectures; software support for reconfigurable components and accelerators; software architectures for low power and low temperature;

Chair: Anuradha Annaswamy, MIT, US, Contact

Co-Chair: Anton Cervin, Lund University, SE, Contact

Topic Members (click to open)

High-level design, optimization and analysis of networked control and switched control systems; control/architecture co-design for distributed embedded systems; formal semantics, verification, model checking and abstraction refinement techniques for control software and systems; simulation and testing; architectures; modeling techniques; architecture-aware controller synthesis; model-based approaches to cyber-physical systems design; reliability-aware design and fault-tolerance; certification issues; specification languages and programming support; case studies in cyber-physical systems such as from automotive systems and avionics, smart buildings and smart grids.