Technical Programme Committee 2013

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Track D: Design, Methods and Tools (click to open)

addressing design automation and design tools for electronic and embedded systems. Emphasis is on methods and tools related to the use of computers in designing products. This includes designer feedback on existing design methods and tools as well as to initiate discussions on requirements of future system architectures, design flows and environments.

Track Chair: Andy Pimentel, University of Amsterdam, NL, Contact


D1 System Specifications, Models, and Methodologies (click to open)

Chair: Christian Haubelt, University of Rostock, DE, Contact

Co-Chair: Dominique Borrione, TIMA Labs, FR, Contact

Topic Members (click to open)

  • Andreas Gerstlauer, University of Texas at Austin, US, Contact
  • Jan Haase, Technical University Vienna, AT, Contact
  • Wolfgang Mueller, Universität Paderborn, DE, Contact
  • Frank Oppenheimer, OFFIS e. V., DE, Contact
  • Francois Pecheux, UPMC/LIP6, FR, Contact
  • Ingo Sander, Royal Institute of Technology, SE, Contact
  • Leandro Indrusiak, University of York, UK, Contact
  • Sander Stuijk, Eindhoven University of Technology, NL, Contact
  • Eugenio Villar, University of Cantabria, ES, Contact

Modeling and specification methodologies for complex, HW-SW embedded systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

D2 System Design, Synthesis and Optimization (click to open)

Chair: jamaatdtu [dot] dk, Contact

Co-Chair: Luciano Lavagno, Politecnico di Torino, IT, Contact

Topic Members (click to open)

  • Rainer Doemer, University of California, Irvine, US, Contact
  • Soonhoi Ha, Seoul National University, KR, Contact
  • Wido Kruijtzer, Synopsys, NL, Contact
  • Sri Parameswaran, UNSW, AU, Contact
  • Sudeep Pasricha, Colorado State University, US, Contact
  • , Contact
  • donatella [dot] sciutoatpolimi [dot] it, Contact
  • Todor Stefanov, Leiden University, NL, Contact
  • Jürgen Teich, University of Erlangen-Nuremberg, DE, Contact
  • Yosinori Watanabe, Cadence Design Systems, US, Contact
  • Jason Xue Chun, City University of Hong Kong, HK, Contact

Synthesis of complete systems, application- and domain-specific synthesis techniques; system-level models for design, optimization and synthesis; hardware/software co-design and partitioning issues; hardware/software interface and communication synthesis; interface-based and correct-by construction designs; system-level scheduling techniques; protocol synthesis and optimization; system optimization for all cost functions (timing, electrical, non-functional); multi-objective, classical and nature-inspired optimization techniques for system level design; large-scale and industrial case studies involving full system optimization and synthesis.

D3 Simulation and Validation (click to open)

Chair: Franco Fummi, Universita' di Verona, IT, Contact

Co-Chair: Mark Zwolinski, University of Southampton, UK, Contact

Topic Members (click to open)

  • Andrea Acquaviva, Politecnico di Torino, IT, Contact
  • Valeria Bertacco, University of Michigan, US, Contact
  • Pallab Dasgupta, Indian Institute of Technology Kharagpur, IN, Contact
  • adrian [dot] evansatiroctech [dot] com, Contact
  • Rand Gray, Intel Corporation, US, Contact
  • Daniel Grosse, University of Bremen, DE, Contact
  • Michael Hsiao, Virginia Tech, US, Contact
  • ioana [dot] vatajeluatuniv-grenoble-alpes [dot] fr, Contact
  • Florian Letombe, SpringSoft, FR, Contact
  • Prabhat Mishra, University of Florida, US, Contact
  • Ronny Morad, IBM Research - Haifa, IL, Contact
  • Edouard Ngoya, Agilent, FR, Contact
  • Jaan Raik, Tallinn University of Technology, Department of Computer Engineering, EE, Contact
  • Pablo Sanchez, University of Cantabria, ES, Contact
  • Alper Sen, Bogazici University, TR, Contact
  • Daryl Stewart, ARM, UK, Contact
  • Shireesh Verma, Conexant Systems Inc., US, Contact

Simulation-based verification; post-silicon validation; hardware/software co-simulation and validation, ATPG for validation; transaction-level validation; semi-formal verification techniques; test bench generation; design error debug and diagnosis; advanced simulation and emulation techniques from system to circuit level; simulation accelerators; multi-domain simulation techniques for mixed systems.

D4 Design of Low Power Systems (click to open)

Chair: Tudor Murgan, Intel, DE, Contact

Co-Chair: Domenik Helms, OFFIS, DE, Contact

Topic Members (click to open)

  • Naehyuck Chang, Seoul National University, KR, Contact
  • Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
  • Wei Huang, IBM Research, US, Contact
  • Antonio J. Acosta-Jimenez, University of Seville/IMSE, ES, Contact
  • Marisa Lopez-Vallejo, UPM, ES, Contact
  • Alberto Macii, Politecnico di Torino, IT, Contact
  • Biswajit Mishra, EPFL, CH, Contact
  • Alberto Nannarelli, DTU, DK, Contact
  • Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
  • Wolfgang Nebel, Oldenburg University and OFFIS, DE, Contact
  • , Contact
  • Mircea Stan, University of Virginia, US, Contact

Design methods, techniques and case studies of low power systems, covering aspects from specification, mapping, new algorithms, system architecture to circuit; including power minimization techniques for analog and digital circuits, HW and SW aspects, power management, batteries, energy harvesting, thermal aware computation and technology aware design aspects in nanometer technologies (i.e., leakage, variability, reliability, 3D stacking, etc);

D5 Power Estimation and Optimization (click to open)

Chair: Massimo Poncino, Politecnico di Torino, IT, Contact

Co-Chair: Jian-Jia Chen, KIT, DE, Contact

Topic Members (click to open)

  • Edith Beigne, CEA-LETI Minatec, FR, Contact
  • Yiran Chen, Seagate Technology, US, Contact
  • William Fornaciari, Politecnico di Milano - DEI, IT, Contact
  • Josef Haid, Infineon, AT, Contact
  • Joerg Henkel, Karlsruhe Institute of Technology, DE, Contact
  • Francesc Moll, Universitat Politècnica de Catalunya, ES, Contact
  • Mauro Olivieri, Sapienza University of Rome, IT, Contact
  • Anand Raghunathan, Purdue University, US, Contact
  • Olivier Sentieys, INRIA - University of Rennes 1, FR, Contact
  • Ranga Vemuri, University of Cincinnati, US, Contact
  • Xiaorui Wang, University of Ohio, US, Contact
  • Chia-Lin Yang, National Taiwan University, TW, Contact

Algorithms, techniques and tools for power and temperature modeling, estimation and optimization of electronic systems applicable at all levels of the design hierarchy, from system-level specification to layout, including software and run-time management.

D6 Emerging Technologies, Systems and Applications (click to open)

Chair: Sanjukta Bhanja, University of South Florida, US, Contact

Co-Chair: Siddharth Garg, University of Waterloo, CA, Contact

Topic Members (click to open)

  • Syed Alam, Everspin Technologies Inc., US, Contact
  • Paul Bogdan, Carnegie Mellon University, US, Contact
  • Dhireesha Kudithipudi, Rochester Institute of Technology, US, Contact
  • Hai Li, University of Pittsburgh, US, Contact
  • Chrysostomos Nicopoulos, University of Cyprus, CY, Contact
  • Michael Niemier, University Of Notre Dame, US, Contact
  • Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact
  • Marco Ottavi, University of Rome "Tor Vergata", IT, Contact
  • Phillip Stanley-Marbell, IBM Research, CH, Contact
  • Guangyu Sun, Peking University, CN, Contact
  • Yvain Thonnart, CEA, LETI, MINATEC, FR, Contact
  • Aida Todri-Sanial, CNRS - LIRMM, FR, Contact
  • Chun-Yao Wang, National Tsing Hua University, TW, Contact
  • Yu Wang, Tsinghua Univ., CN, Contact

System design methods, models of computation, and case studies for emerging applications: ambient intelligence, ubiquitous computing, wearable computing, bio-inspired computation; Design automation flows and case studies for upcoming and future technologies: MEMS, BIOMEMS, Lab-on-a-chip, 3D integration, nanoscale and molecular scale circuits and systems.

D7 Formal Methods and Verification (click to open)

Chair: Gianpiero Cabodi, Politecnico di Torino, IT, Contact

Co-Chair: Jason Baumgartner, IBM Corporation, US, Contact

Topic Members (click to open)

  • Armin Biere, Universitaet Linz, AT, Contact
  • Alessandro Cimatti, FBK-irst (Fondazione Bruno Kessler - Center for Information technology), IT, Contact
  • Barbara Jobstmann, VERIMAG, FR, Contact
  • Joao Marques-Silva, University College Dublin, IE, Contact
  • Fahim Rahim, Atrenta, FR, Contact
  • Julien Schmaltz, Open University, NL, Contact
  • Christoph Scholl, University Freiburg, DE, Contact
  • Thomas Wahl, Northeastern University Boston, US, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem-proving, abstraction and decomposition techniques, and real-time verification); technologies supporting formal verification (including SMT, SAT, BDD, ATPG, and related work); semi-formal verification techniques; applications and case studies; formal verification of IPs, SoCs, cores, real-time and embedded systems; verification in practice, namely the integration of verification into the design flow; challenges of multi-cores, both as verification targets and as verification host platforms.

D8 Networks-on-Chip (click to open)

Chair: Federico Angiolini, iNoCs, CH, Contact

Co-Chair: Fabien Clermidy, CEA-LETI, FR, Contact

Topic Members (click to open)

  • Paul Ampadu, University of Rochester, US, Contact
  • Luca Benini, Università di Bologna, IT, Contact
  • Davide Bertozzi, University of Ferrara, IT, Contact
  • Luca Carloni, Columbia University, US, Contact
  • Érika Cota, UFRGS, BR, Contact
  • Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
  • Josè Flich, Universidad Politecnica de Valencia, ES, Contact
  • Kees Goossens, Eindhoven Univ. of Technology, NL, Contact
  • Andreas Hansson, ARM Ltd, UK, Contact
  • Shaahin Hessabi, Sharif University of Technology, IR, Contact
  • Axel Jantsch, KTH, SE, Contact
  • Jung Ho Ahn, Seoul National University, KR, Contact
  • Hiroki Matsutani, Keio University, JP, Contact
  • Steven Nowick, Columbia University, US, Contact
  • Pascal VIVET, CEA-LETI, FR, Contact
  • Sungjoo Yoo, POSTECH, KR, Contact

Architecture, modeling and design techniques for Networks-on-Chips; design methods for the on-chip interconnection network: topology, switching, routing and flow control methods; architecture and design for fault-tolerance, reliability enhancement, quality of service, dynamic voltage and frequency scaling; techniques and methodologies for NoC testing; GALS synchronization architectures for NoCs; physical design techniques and methodologies; integration of external interfaces/memory controllers with NoCs; cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; programming models for NoC-based platforms; industrial applications of NoCs; design of NoCs based on alternative technologies such as photonics/optics, wireless, 3D stacking.

D9 Architectural and Micro-Architectural Design (click to open)

Chair: Laura Pozzi, University of Lugano, CH, Contact

Co-Chair: Tulika Mitra, National University of Singapore, SG, Contact

Topic Members (click to open)

  • Todd Austin, University of Michigan, US, Contact
  • Mladen Berekovic, TU Braunschweig, DE, Contact
  • Bjorn De Sutter, Ghent University, BE, Contact
  • Mike Ferdman, Stony Brook University, US, Contact
  • Diana Franklin, UC Santa Barbara, US, Contact
  • Georgi Gaydadjiev, Chalmers University, SE, Contact
  • Nikos Hardavellas, Northwestern University, US, Contact
  • Rakesh Kumar, University of Illinois, US, Contact
  • Yun (eric) Liang, Peking University, CN, Contact
  • Andreas Moshovos, University of Toronto, CA, Contact
  • Dionisios Pnevmatikatos, Technical University of Crete, GR, Contact
  • Hsien-Hsin Lee, Georgia Institute of Technology, US, Contact
  • John Sartori, University of Minnesota, US, Contact
  • Toshinori Sato, Fukuoka University, JP, Contact
  • Zili Shao, Hong Kong Polytechnic University, HK, Contact
  • Cristina SILVANO, Politecnico di Milano, IT, Contact
  • Jian Wu, Marvell Semiconductor, US, Contact
  • Sami Yehia, Intel, US, Contact

Architectural and micro-architectural design techniques, memory systems, power and energy efficient architectures, multi/many-core architectures, multithreading techniques and support for parallelism, modeling and performance analysis, advanced computer architecture for application-specific applications, special purpose processors and accelerators, future and emerging architectures.

D10 Architectural and High-Level Synthesis (click to open)

Topic Members (click to open)

    Synthesis of hardware systems from high-level descriptions; hardware-centric system-level synthesis, analysis, and optimization; high-level language hardware description, parsing and compilation; scheduling, allocation, and binding of operations, variables, and transfers; automatic design and optimization of data-paths, dedicated memory and communication structures, and controllers; performance, cost, and power driven architectural-level optimizations; application-specific processor generation, automatic processor customization, and accelerator synthesis.

    D11 Reconfigurable Computing (click to open)

    Chair: Fadi Kurdahi, University of California at Irvine, US, Contact

    Co-Chair: Marco Platzner, University of Paderborn, DE, Contact

    Topic Members (click to open)

    • koen bertels, Delft University of Technology, NL, Contact
    • Peter Cheung, Imperial College, UK, Contact
    • Fabrizio Ferrandi, Politecnico di Milano, IT, Contact
    • Diana Goehringer, Ruhr-University Bochum, DE, Contact
    • Yajun Ha, National University of Singapore, SG, Contact
    • Enno Luebbers, Intel Open Lab Munich, DE, Contact
    • Patrick Lysaght, Xilinx, US, Contact
    • Walid Najjar, UC Riverside, US, Contact
    • Smail Niar, University of Valenciennes, FR, Contact
    • Mazen Saghir, Texas A&M University, QA, Contact
    • Jarmo Takala, Tampere University of Technology, FI, Contact

    Statically and dynamically reconfigurable and reprogrammable systems and components: platforms and architectures, FPGAs, reconfigurable processors, design methods and tools for reconfigurable computing and communication, applications.

    D12 Logic Synthesis and Timing Analysis (click to open)

    Chair: Jordi Cortadella, Universitat Politecnica de Catalunya, ES, Contact

    Co-Chair: José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact

    Topic Members (click to open)

    • Michel Berkelaar, Delft University of Technology, NL, Contact
    • Valentina Ciriani, University of Milano, IT, Contact
    • Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
    • John Hayes, University of Michigan, US, Contact
    • victor kravets, IBM, US, Contact
    • Sanjay Kumar, Synopsys, US, Contact
    • Davide Pandini, STMicroelectronics, IT, Contact
    • Tiziano Villa, University of Verona, IT, Contact
    • Vladimir Zolotov, IBM T.J. Watson Research Center, US, Contact

    Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design, statistical timing analysis, timing closure; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; PLD and FPGA synthesis; arithmetic circuits.

    D13 Physical Design and Verification (click to open)

    Chair: Ralph Otten, TU Eindhoven, NL, Contact

    Co-Chair: Azadeh Davoodi, University of Wisconsin - Madison, US, Contact

    Topic Members (click to open)

    • Cheng-Kok Koh, Purdue University, US, Contact
    • Jens Lienig, Technical University of Dresden, DE, Contact
    • Michael Orshansky, University of Texas at Austin, US, Contact
    • Sven Peyer, IBM, DE, Contact
    • Jose Pineda, NXP / TU Eindhoven, NL, Contact
    • Carl Sechen, UT Dallas, US, Contact
    • Rasit Topaloglu, IBM US, US, Contact
    • Evangeline Young, The Chinese University of Hong Kong, HK, Contact

    Floorplanning; automatic place and route; module generation; design rule checking and layout characterization; electrical verification; problems in deep sub-micron and high-speed design; interconnect-driven and performance-driven layout; process technology developments; design for manufacturability.

    D14 Analog and Mixed-Signal Systems and Circuits (click to open)

    Chair: Catherine Dehollain, EPFL, CH, Contact

    Co-Chair: Günhan Dündar, Boğaziçi University, TR, Contact

    Topic Members (click to open)

    • Francisco Fernandez, IMSE, CSIC and University of Sevilla, ES, Contact
    • Georges Gielen, Katholieke Universiteit Leuven, BE, Contact
    • Christoph Grimm, TU Vienna, AT, Contact
    • Joachim Haase, Fraunhofer EAS, DE, Contact
    • Lars Hedrich, University of Frankfurt, DE, Contact
    • Tom Kazmierski, University of Southampton, UK, Contact
    • marie-Minerve Louerat, UNiversity Pierre & Marie Curie, LIP6, FR, Contact
    • Dominique MORCHE, CEA-LETI, FR, Contact
    • peter wilson, university of southampton, UK, Contact

    CAD for analogue and mixed-signal circuits and systems: Layout, Topology generation, Architecture and System Synthesis, Modeling of AMS circuits and systems, Modeling strategies, Modeling of complex analogue mixed-signal systems, Model generation, Formal and Symbolic Techniques; Languages for AMS circuits and systems: VHDL-AMS, Verilog-AMS, SystemC-AMS, Matlab/Simulink, Ptolomy; Innovative circuit topologies and architectures: Topologies/architectures that increase robustness, Topologies/architectures that increase re-usability; Modeling and Synthesis of Multi-Domain systems: MEMS, Energy Harvesting Systems.

    D15 Modeling and Design for Signal and Power Integrity (click to open)

    Chair: Stefano Grivet-Talocia, Politecnico di Torino, IT, Contact

    Co-Chair: Joungho Kim, KAIST, KR, Contact

    Topic Members (click to open)

    • Luca Daniel, Massachusetts Institute of Technology, US, Contact
    • sung kyu lim, georgia tech, US, Contact
    • Dries Vande Ginste, University of Ghent, BE, Contact

    Modeling, characterization and analysis of on and off chip interconnects, and packaging; modeling, design, and characterization of Through Silicon Vias (TSV), 3D Interconnects, and interposer; wireless interconnects via capacitive/inductive coupling; modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate; EMC issues in interconnects: electromagnetic emission, susceptibility and compatibility; chip-package co-design, modeling, and noise coupling issues in 3D IC and packages; high-speed channel and equalizer modeling, design, and measurement; macro-modeling, behavioral, and reduced order modeling.

    Track A: Application Design (click to open)

    is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as innovative design methodologies and applications of specific design technologies. Contributions should illustrate state-of-the-art or record breaking designs, which will provide viable solutions in tomorrow's silicon and embedded systems. In topic A7, there is the opportunity to submit short, 2-page papers, that relate to industrial research and practice.

    Track Chair: David Atienza, EPFL, CH, Contact


    A1 Green Computing Systems (click to open)

    Chair: Tajana Simunic Rosing, UCSD, US, Contact

    Co-Chair: AYSE COSKUN, Boston University, US, Contact

    Topic Members (click to open)

    • Andreas Burg, EPFL, CH, Contact
    • Michael Kauschke, Intel GmbH, DE, Contact
    • Qinru Qiu, Syracuse University, US, Contact

    Practical design experiences in industrial projects or academic projects with high industrial relevance targeting high performance, parallel, or information technology systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, data centers, and cyber-physical systems. Topics of interest include, but are not limited to: new software architectures for parallel systems, cloud computing approaches, energy-efficient memory architectures, low-power multi-core architectures and management techniques, new communication/interconnect architectures, novel energy-efficient system designs, energy efficient programming techniques, or adaptive / learning-based methods for improving energy efficiency.

    A2 Communication, Consumer and Multimedia Systems (click to open)

    Chair: Frank Kienle, Technical University of Kaiserslautern, DE, Contact

    Co-Chair: Theocharis Theocharides, University of Cyprus, CY, Contact

    Topic Members (click to open)

    • Amer Baghdadi, TELECOM Bretagne, FR, Contact
    • Christos Bouganis, Imperial College, UK, Contact
    • David Gnaedig, TurboConcept (company), FR, Contact
    • Ilker Hamzaoglu, Sabanci University, TR, Contact
    • Guido Masera, Politecnico di Torino, IT, Contact
    • Emil Matus, Technische Universität Dresden, DE, Contact
    • Steffen Paul, Unversity Bremen, DE, Contact
    • Sergio Saponara, University of Pisa, IT, Contact
    • Ioannis Sourdis, Chalmers Univeristy of Technology, SE, Contact

    Practical design experience for communication, multimedia and consumer systems like smartphones, smart-books/tablets; examples are digital integrated circuits design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software defined radio systems; embedded systems design in the field of audio, video and vision domain; Application Specific Processors (ASP)/ Digital Signal Processors (DSP) for these domains.

    A3 Transportation, Management and Energy Generation Systems (click to open)

    Chair: Davide Brunelli, University of Trento, IT, Contact

    Co-Chair: Bart Vermeulen, NXP Semiconductors, NL, Contact

    Topic Members (click to open)

    • Juergen Becker, KIT - Karlsruher Institut für Technolgie, DE, Contact
    • Geoff Merrett, University of Southampton, UK, Contact
    • Emanuel Popovici, National University of Ireland, IE, Contact
    • Haibo Zeng, General Motors, US, Contact

    Practical design experiences for transportation and energy generation and distribution systems and applications: analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures and integrated sensors and transducers, RF architectures, networks of systems, energy scavenging and harvesting methods from environmental sources. Practical applications of design methods to transportation and energy systems, including models, methods and tools, design of hardware and software components, architecture analysis and optimization, component-oriented design and system-level analysis and validation. Hardware and software solutions to address energy management: components of different nature with focus on energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems and optimization of system energy efficiency.

    A4 Medical and Healthcare Systems (click to open)

    Chair: , Contact

    Co-Chair: Martino Ruggiero, University of Bologna, IT, Contact

    Topic Members (click to open)

    • efarellaatfbk [dot] eu, Contact
    • Ani Nahapetian, UCLA, US, Contact
    • francisco [dot] rinconatepfl [dot] ch, Contact

    Medical, healthcare, and life science applications require increasingly smarter and smaller devices and personalized medicine will lead to a significant increase in both complex lab solutions as well as a myriad of consumer-like disposable devices. Application examples such as multi-physics nano-bio transducers, cellular interfacing chips, multi-parameter biosensors, pharmaceutical assay chips, implantable and wearable wireless devices for patient monitoring and therapy will reveal complex heterogeneous microsystem designs and design methods, multi-level modeling approaches, co-development of design and process technology.

    A5 Secure Systems (click to open)

    Chair: Patrick Schaumont, Virginia Tech, US, Contact

    Co-Chair: Guido Bertoni, STMicroelectronics, IT, Contact

    Topic Members (click to open)

    • Ray Cheung, City University of Hong Kong, HK, Contact
    • Viktor Fischer, Laboratoire Hubert Curien, FR, Contact
    • Wieland Fischer, Infineon, DE, Contact
    • Tim Güneysu, Ruhr University Bochum, DE, Contact
    • Paolo Maistri, TIMA Laboratory, FR, Contact
    • Maire O'Neill, Queen's University Belfast, UK, Contact
    • Jerome Quevremont, Thales, FR, Contact
    • Francesco Regazzoni, Université catholique de Louvain and ALaRI, CH, Contact
    • Ingrid Verbauwhede, KU Leuven and UCLA, BE, Contact

    Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

    A6 Reliable and Reconfigurable Systems (click to open)

    Chair: jayalaatucm [dot] es, Contact

    Co-Chair: Marco D. Santambrogio, Politecnico di Milano, IT, Contact

    Topic Members (click to open)

    • Andrea Calimera, Politecnico di Torino, IT, Contact
    • , Contact
    • Oliver Pell, Maxeler Technologies, UK, Contact
    • , Contact
    • Vincenzo Rana, Politecnico di Milano, IT, Contact
    • Marian Verhelst, KULeuven - ESAT - MICAS, BE, Contact

    This topic covers the area of reliable and adaptive systems for practical applications. The scope of this topic includes, but not limited to, the development, optimization and practical application mechanisms to compensate for aging and temperature, development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

    A7 Industrial Experiences Brief Papers (click to open)

    Chair: Ahmed Jerraya, CEA Leti, FR, Contact

    Co-Chair: Roberto Zafalon, STMicroelectronics, IT, Contact

    Topic Members (click to open)

    • Wolfgang Dettmann, Infineon, DE, Contact
    • Marco Ottella, Biltron, IT, Contact

    Short or brief papers with a limit of two pages are solicited that relate to industrial research and practice: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanism. Product presentations and announcements are strongly discouraged and will not be considered for publication.

    Track T: Test and Reliability (click to open)

    addressing design-oriented embedded test solutions as well as defect analysis, modeling, test generation and silicon debugging. Emphasis is on both system- and chip-level test.

    Track Chair: Erik Jan Marinissen, IMEC, BE, Contact


    T1 Test for Defects, Variability, and Reliability (click to open)

    Chair: Bram Kruseman, NXP Semiconductors, NL, Contact

    Co-Chair: Jaume Segura, Universitat de les Illes Balears, ES, Contact

    Topic Members (click to open)

    • Kanak Agarwal, IBM Corp, US, Contact
    • Robert Aitken, ARM, US, Contact
    • Sandeep Gupta, University of Southern California, US, Contact
    • Kuen-Jong Lee, National Cheng Kung University, TW, Contact
    • Markus Rudack, Intel Mobile Communications GmbH, DE, Contact
    • Medhi Tahoori, KIT, DE, Contact

    Identification, characterization and modeling of defects, faults and degradation mechanisms; defect-based fault analysis, simulation and ATPG of defect-based faults; reliability analysis and modeling techniques, FMEA and physics of failure; test for noise and uncertainty; design-for-reliability and design-for-variability and their impact on test; test and reliability of redundant systems; test and reliability issues in the presence of leakage; challenges of ultra low-power design on test and reliability; modeling and test techniques for physical sources of errors such as process, voltage and temperature variations; error-resilient nano-design systems.

    T2 Test Generation, Simulation, and Diagnosis (click to open)

    Chair: Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact

    Co-Chair: Bernd Becker, University of Freiburg, DE, Contact

    Topic Members (click to open)

    • , Contact
    • Nicola Nicolici, McMaster University, CA, Contact
    • Frank Poehl, Intel, DE, Contact
    • matteo sonza reorda, politecnico di torino - DAUIN, IT, Contact
    • Arnau Virazel, LIRMM / Univ. Montpellier, FR, Contact
    • Xiaoqing Wen, Kyushu Institute of Technology, JP, Contact

    Test pattern generation; high-level TPG; delay TPG; fault simulation; test generation for validation, debug and diagnosis; low-power TPG; TPG for memories and FPGAs.

    T3 Test for Mixed-Signal, Analog, RF, MEMS (click to open)

    Chair: Abhijit Chatterjee, Georgia Tech, US, Contact

    Co-Chair: haralampos [dot] stratigopoulosatlip6 [dot] fr, Contact

    Topic Members (click to open)

    • Hans Kerkhoff, University of Twente / CTIT, NL, Contact
    • Gildas Leger, IMSE-CNM-CSIC, ES, Contact
    • Sebastian Sattler, University Erlangen-Nuermberg, DE, Contact

    Test techniques for mixed-signal, RF and multi-GHz electronics; test techniques for embedded MEMS/bioMEMS/MOEMS sensors and actuators; assembly engineering for SiP/SoC/SoP/PoP; Failure modeling and analysis techniques; defect characterization and fault modeling; fault simulation and test generation algorithms; DfT/DfM/DfY/DfR (DfX) techniques; BIST; test coverage metrics and statistical modeling; effective defect screening techniques; diagnosis and self-repair.

    T4 Test Access, Design-for-Test, Test Compression, System Test (click to open)

    Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

    Co-Chair: Rohit Kapur, Synopsys, US, Contact

    Topic Members (click to open)

    • Davide Appello, ST Microelectronics, IT, Contact
    • Luigi DILILLO, LIRMM, FR, Contact
    • Marie-Lise Flottes, LIRMM, FR, Contact
    • Peter Harrod, ARM Ltd, UK, Contact
    • Paolo PRINETTO, Politecnico di Torino, IT, Contact
    • Nur Touba, University of Texas at Austin, US, Contact
    • Jerzy Tyszer, Poznan University of Technology, PL, Contact
    • Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact

    Design-for-test, -debug, and -manufacturability; built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DfT techniques, DfT for secure systems, DfT economics. Testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, board, system; testing 3D (TSV-based) chips; Network-on-Chip test; system-level debug and validation; hardware/software system test; processor based test; infrastructure IP; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies.

    T5 On-Line Testing and Fault Tolerance (click to open)

    Chair: Cecilia Metra, University of Bologna, IT, Contact

    Co-Chair: Lorena Anghel, TIMA, FR, Contact

    Topic Members (click to open)

    • Jaume Abella, Barcelona Supercomputing Center, ES, Contact
    • Cristiana Bolchini, Polimi, IT, Contact
    • Giorgio Di Natale, LIRMM, FR, Contact
    • Fabrizio Lombardi, Northeastern University, US, Contact
    • Yiorgos Makris, Dallas University, US, Contact
    • Diana Marculescu, Carnegie Mellon University, US, Contact
    • Michael Nicolaidis, TIMA, FR, Contact
    • Antonis Paschalis, University of Athens, GR, Contact
    • Xavier Vera, Intel, ES, Contact

    Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuits and systems design; dependability evaluation, dependable system design; redundant systems design; hardware/software recovery; self-repair; fault tolerance; on-line testing and fault tolerance for industrial applications.

    Track E: Embedded Systems Software (click to open)

    is devoted to modeling, analysis, design and deployment of Embedded Software. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on embedded software platforms, software integration, adaptive real-time systems, and dependable systems.

    Track Chair: Petru Eles, Linköping University, SE, Contact


    E1 Real-time, Networked, and Dependable Systems (click to open)

    Chair: Giuseppe Lipari, ENS-Cachan, FR, Contact

    Co-Chair: Stefan M. Petters, CISTER-ISEP, IPP, PT, Contact

    Topic Members (click to open)

    • Luis Almeida, University of Porto, PT, Contact
    • Sebastian Fischmeister, University of Waterloo, CA, Contact
    • Marc Geilen, TU Eindhoven, NL, Contact
    • Gregor Gössler, INRIA, FR, Contact
    • Joel Goossens, Universite Libre de Bruxelles, BE, Contact
    • Armin Groesslinger, Passau University, DE, Contact
    • Raimund Kirner, University of Hertfortshire, UK, Contact
    • Chang-Gun Lee, Seoul National University, KR, Contact
    • Xue Liu, McGill University, CA, Contact
    • Michael Paulitsch, EADS, DE, Contact
    • Binoy Ravindran, Virginia Tech, US, Contact
    • Dakai Zhu, University of Texas at San Antonio, US, Contact

    Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; tools and design methods for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications;

    E2 Compilers and Software Synthesis for Embedded Systems (click to open)

    Chair: Bjoern Franke, University of Edinburgh, UK, Contact

    Co-Chair: Heiko Falk, Ulm University, DE, Contact

    Topic Members (click to open)

    • Alain Darte, ENS Lyon - INRIA, FR, Contact
    • Frank Hannig, University of Erlangen-Nuremberg, DE, Contact
    • Florence Maraninchi, Grenoble INP / Ensimag & VERIMAG, FR, Contact
    • Rodric Rabbah, IBM Research, US, Contact
    • David Whalley, Florida State University, US, Contact

    Software synthesis; compilers; code generation; dynamic compilation for embedded systems; software generation tool chain; software environment and generation for design space exploration (compilers, simulators, synthesis tools); retargetable compilers for MPSOC and reconfigurable platforms; compilers for embedded multi-core systems; compiler and software synthesis for low power

    E3 Model-Based Design and Verification for Embedded Systems (click to open)

    Chair: Wang Yi, Uppsala University, SE, Contact

    Co-Chair: Saddek Bensalem, Université Joseph Fourier, FR, Contact

    Topic Members (click to open)

    • Christoph Kirsch, University of Salzburg, AT, Contact
    • Kai Lampka, Uppsala University, SE, Contact
    • Marc Pouzet, Ecole normale superieure, FR, Contact
    • Natasha Sharygina, University of Lugano, CH, Contact
    • Oleg Sokolsky, University of Pennsylvania, US, Contact
    • Farn Wang, National Taiwan University, TW, Contact

    Model-based methods for embedded system design; verification of embedded systems; model-based software architectures; model-based design for control applications; model-based software testing, software/system integration and deployment; tools for model-based embedded system design; software verification;

    E4 Embedded Software Architectures (click to open)

    Chair: Gabriela Nicolescu, Ecole Polytechnique de Montreal, CA, Contact

    Co-Chair: Oliver Bringmann, FZI / University of Tuebingen, DE, Contact

    Topic Members (click to open)

    • Gero Dittmann, IBM, DE, Contact
    • Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
    • Huy-Nam Nguyen, Bull S.A.S., FR, Contact
    • Alex Orailoglu, UC San Diego, US, Contact
    • Frank Slomka, Ulm University, DE, Contact

    Software architectures for MPSoC, multi/many-core and GPU-based systems; programming languages for embedded MPSoC, multi/many-core and GPU-based systems; virtualization for embedded systems, including safety and security aspects; resources constrained middleware and Run-Time Environment (RTE) architectures; software support for reconfigurable components and accelerators; software architectures for low power and low temperature;

    E5 Cyber-Physical Systems (click to open)

    Chair: Anuradha Annaswamy, MIT, US, Contact

    Co-Chair: Anton Cervin, Lund University, SE, Contact

    Topic Members (click to open)

    • Rolf Ernst, TU Braunschweig, DE, Contact
    • Joao Hespanha, UC Santa Barbara, US, Contact
    • George Pappas, University of Pennsylvania, US, Contact
    • Paulo Tabuada, UC Los Angeles, US, Contact

    High-level design, optimization and analysis of networked control and switched control systems; control/architecture co-design for distributed embedded systems; formal semantics, verification, model checking and abstraction refinement techniques for control software and systems; simulation and testing; architectures; modeling techniques; architecture-aware controller synthesis; model-based approaches to cyber-physical systems design; reliability-aware design and fault-tolerance; certification issues; specification languages and programming support; case studies in cyber-physical systems such as from automotive systems and avionics, smart buildings and smart grids.