DATE 1998 Author Index

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[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]


A

Abadir, M.S.
Abstract icon PDF icon Measuring the Effectiveness of Various Design Validation Approaches for PowerPCTMMicroprocessor Arrays [p 273]
Adler, T.
Abstract icon PDF icon An Interactive Router for Analog IC Design [p 414]
Agsteiner, K.
Abstract icon PDF icon An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Al-Khalili, D.
Abstract icon PDF icon VHDL Modelling and Analysis of Fault Secure Systems [p 148]
Allara, A.
Abstract icon PDF icon A Model for System-Level Timed Analysis and Profiling [p 204]
Andrews, M.
Abstract icon PDF icon Power and Timing Modeling for ASIC Designs [p 969]
Antola, A.
Abstract icon PDF icon A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
Aourid, S.
Abstract icon PDF icon Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Arsintescu, B.G.
Abstract icon PDF icon Constraints Space Management for the Layout of Analog IC's [p 971]
Artigas, J.I.
Abstract icon PDF icon VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
Arts, H.
Abstract icon PDF icon PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
Arz, U.
Abstract icon PDF icon Core Interconnect Testing Hazards [p 953]
Auvergne, D.
Abstract icon PDF icon Temperature Effect on Delay for Low Voltage Applications [p 680]
Avedillo, M.J.
Abstract icon PDF icon A Dynamic Model for the State Assignment Problem [p 835]
Ayuda, L.
Abstract icon PDF icon VHDL Teamwork, Organization Units and Workspace Management [p 297]
Azaïs, F.
Abstract icon PDF icon Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]

B

Banerjee, P.
Abstract icon PDF icon PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
Barke, E.
Abstract icon PDF icon A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances [p 649]
Abstract icon PDF icon Path Verification Using Boolean Satisfiability [p 965]
Barragán, L.A.
Abstract icon PDF icon VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
Barriga, A.
Abstract icon PDF icon XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Basu, A.
Abstract icon PDF icon Register-Constrained Address Computation in DSP Programs [p 929]
Baur, U.
Abstract icon PDF icon A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Becker, U.
Abstract icon PDF icon A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Benini, L.
Abstract icon PDF icon Characterization-Free Behavioral Power Modeling [p 767]
Abstract icon PDF icon Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Berkelaar, M.R.C.M.
Abstract icon PDF icon An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
Bertrand, Y.
Abstract icon PDF icon Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]
Bisdounis, L.
Abstract icon PDF icon Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Blaauw, D.
Abstract icon PDF icon CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Bogliolo, A.
Abstract icon PDF icon Characterization-Free Behavioral Power Modeling [p 767]
Bogue, T.
Abstract icon PDF icon Built-In Self-Test with an Alternating Output [p 180]
Bolchini, C.
Abstract icon PDF icon Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
Böttger, J.
Abstract icon PDF icon An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Brayton, R.K.
Abstract icon PDF icon Combinational Verification Based on High-Level Functional Specifications [p 803]
Breuer, M.A.
Abstract icon PDF icon Scheduling and Module Assignment for Reducing BIST Resources [p 66]
Brglez, F.
Abstract icon PDF icon Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Bringmann, O.
Abstract icon PDF icon Cross-Level Hierarchical High-Level Synthesis [p 451]
Buchenrieder, K.
Abstract icon PDF icon A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]

C

Calin, T.
Abstract icon PDF icon Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
Calvez, J.P.
Abstract icon PDF icon A Programmable Multi-Language Generator for CoDesign [p 927]
Carrabina-Bordoll, J.
Abstract icon PDF icon On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits [p 624]
Castellví, A.
Abstract icon PDF icon Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Catthoor, F.
Abstract icon PDF icon Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology Versus Design Methodology Solutions [p 709]
Cerny, E.
Abstract icon PDF icon Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Chakradhar, S.T.
Abstract icon PDF icon State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits [p 577]
Chandramouli, V.
Abstract icon PDF icon AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
Chang, D.
Abstract icon PDF icon Functional Scan Chain Testing [p 278]
Chang, S.-C.
Abstract icon PDF icon On Removing Multiple Redundancies in Combinational Circuits [p 738]
Chatzigeorgiou, A.
Abstract icon PDF icon Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]
Chen, C.-T.
Abstract icon PDF icon Architectural Rule Checking for High-Level Synthesis [p 949]
Chen, R.M.M.
Abstract icon PDF icon MCM Interconnect Design Using Two-Pole Approximation [p 544]
Cheng, D.I.
Abstract icon PDF icon On Removing Multiple Redundancies in Combinational Circuits [p 738]
Cheng, K.-T.
Abstract icon PDF icon Functional Scan Chain Testing [p 278]
Abstract icon PDF icon Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits [p 698]
Cheung, H.
Abstract icon PDF icon Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Choi, H.
Abstract icon PDF icon Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
Chou, M.
Abstract icon PDF icon Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
Chu, C.C.N.
Abstract icon PDF icon A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing [p 479]
Conradi, P.
Abstract icon PDF icon A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
Coors, M.
Abstract icon PDF icon FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Coppens, J.
Abstract icon PDF icon VHDL Modelling and Analysis of Fault Secure Systems [p 148]
Corno, F.
Abstract icon PDF icon Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Abstract icon PDF icon Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Cortadella, J.
Abstract icon PDF icon Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
Costa, J.P.
Abstract icon PDF icon Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
Cota, E.F.
Abstract icon PDF icon Microsystems Testing: An Approach and Open Problems [p 524]
Coudert, O.
Abstract icon PDF icon A New Paradigm for Dichotomy-Based Constrained Encoding [p 830]
Courtois, B.
Abstract icon PDF icon Microsystems Testing: An Approach and Open Problems [p 524]
Crespo, J.
Abstract icon PDF icon ATM Traffic Shaper: ATS [p 96]
Crossland, W.A.
Abstract icon PDF icon Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

D

Daga, J.M.
Abstract icon PDF icon Temperature Effect on Delay for Low Voltage Applications [p 680]
Dave, B.P.
Abstract icon PDF icon CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]
de Armas, V.
Abstract icon PDF icon A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
de Jong, G.
Abstract icon PDF icon Efficient Verification Using Generalized Partial Order Analysis [p 782]
de la Torre, E.
Abstract icon PDF icon Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
De Loore, B.
Abstract icon PDF icon IP-Based System-on-a-Chip Design [p 290]
De Micheli, G.
Abstract icon PDF icon Characterization-Free Behavioral Power Modeling [p 767]
Abstract icon PDF icon Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Deicke, J.
Abstract icon PDF icon From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Dharchoudhury, A.
Abstract icon PDF icon CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Diaz, J.C.
Abstract icon PDF icon ATM Traffic Shaper: ATS [p 96]
Doboli, A.
Abstract icon PDF icon Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Donnay, S.
Abstract icon PDF icon Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Drechsler, R.
Abstract icon PDF icon Dynamic Minimization of Word-Level Decision Diagrams [p 612]
Dröge, G.
Abstract icon PDF icon EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
Duarte, R.O.
Abstract icon PDF icon Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]
Dutt, N.D.
Abstract icon PDF icon Data Cache Sizing for Embedded Processor Applications [p 925]

E

Ecküller, J.
Abstract icon PDF icon Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
Economakos, G.
Abstract icon PDF icon AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]
Eles, P.
Abstract icon PDF icon Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Ellis, A.
Abstract icon PDF icon Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Eppler, W.
Abstract icon PDF icon High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Eshraghian, K.
Abstract icon PDF icon Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

F

Fassnacht, U.
Abstract icon PDF icon Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset [p 325]
Favalli, M.
Abstract icon PDF icon Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
Feldmann, P.
Abstract icon PDF icon Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Padé Approximation [p 530]
Fernández, M.
Abstract icon PDF icon Correct High-Level Synthesis: A Formal Perspective [p 977]
Ferrandi, F.
Abstract icon PDF icon Power Estimation of Behavioral Descriptions [p 762]
Figueras, J.
Abstract icon PDF icon RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
Abstract icon PDF icon Estimation of the Defective IDDQCaused by Shorts in Deep-Submicron CMOS ICs [p 490]
Fischer, T.
Abstract icon PDF icon High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Flottes, M.L.
Abstract icon PDF icon Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Fornaciari, W.
Abstract icon PDF icon A Model for System-Level Timed Analysis and Profiling [p 204]
Freund, R.W.
Abstract icon PDF icon Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Padé Approximation [p 530]
Fummi, F.
Abstract icon PDF icon Power Estimation of Behavioral Descriptions [p 762]
Furber, S.B.
Abstract icon PDF icon The Design of an Asynchronous VHDL Synthesizer [p 44]

G

García, J.I.
Abstract icon PDF icon VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
García, M.
Abstract icon PDF icon Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Garte, D.
Abstract icon PDF icon A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
Gasteier, M.
Abstract icon PDF icon Generation of Interconnect Topologies for Communication Synthesis [p 36]
Gemmeke, H.
Abstract icon PDF icon High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Gerlach, J.
Abstract icon PDF icon A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment [p 226]
Ghosh, D.
Abstract icon PDF icon Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Gielen, G.
Abstract icon PDF icon Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Glesner, M.
Abstract icon PDF icon Generation of Interconnect Topologies for Communication Synthesis [p 36]
Goldberg, E.I.
Abstract icon PDF icon Combinational Verification Based on High-Level Functional Specifications [p 803]
Gómez, J.-A.
Abstract icon PDF icon Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Gong, J.
Abstract icon PDF icon Architectural Rule Checking for High-Level Synthesis [p 949]
Gössel, M.
Abstract icon PDF icon Built-In Self-Test with an Alternating Output [p 180]
Goutis, C.E.
Abstract icon PDF icon Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Gräb, H.
Abstract icon PDF icon Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
Grabinski, H.
Abstract icon PDF icon Core Interconnect Testing Hazards [p 953]
Graeb, H.E.
Abstract icon PDF icon Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
Grimm, C.
Abstract icon PDF icon Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
Grode, J.
Abstract icon PDF icon Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
Gröpl, M.
Abstract icon PDF icon Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
Grötker, T.
Abstract icon PDF icon A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
Grout, I.
Abstract icon PDF icon An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Gschwind, M.
Abstract icon PDF icon Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
Guo, R.
Abstract icon PDF icon Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
Gupta, R.K.
Abstract icon PDF icon An Algorithm to Determine Mutually Exclusive Operations in Behavioral Descriptions [p 457]
Gupta, S.K.
Abstract icon PDF icon Scheduling and Module Assignment for Reducing BIST Resources [p 66]

H

Ha, S.
Abstract icon PDF icon Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
Haase, J.
Abstract icon PDF icon A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Hagelauer, R.
Abstract icon PDF icon Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base [p 931]
Hamilton, S.N.
Abstract icon PDF icon Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
Hansen, C.
Abstract icon PDF icon Verification by Simulation Comparison Using Interface Synthesis [p 436]
Harlow III, J.
Abstract icon PDF icon Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Hedrich, L.
Abstract icon PDF icon A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances [p 649]
Hein, S.
Abstract icon PDF icon Embedded DRAM Architectural Trade-Offs [p 704]
Heineken, H.T.
Abstract icon PDF icon Design-Manufacturing Interface: Part I -- Vision [p 550]
Abstract icon PDF icon Design-Manufacturing Interface: Part II -- Applications [p 557]
Abstract icon PDF icon Performance-Manufacturability Tradeoffs in IC Design [p 563]
Hellebrand, S.
Abstract icon PDF icon Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
Heller, D.
Abstract icon PDF icon A Programmable Multi-Language Generator for CoDesign [p 927]
Helvig, C.S.
Abstract icon PDF icon Improved Approximation Bounds for the Group Steiner Problem [p 406]
Hemani, A.
Abstract icon PDF icon Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
Hermida, R.
Abstract icon PDF icon Correct High-Level Synthesis: A Formal Perspective [p 977]
Hetzel, A.
Abstract icon PDF icon A Sequential Detailed Router for Huge Grid Graphs [p 332]
Higuchi, K.
Abstract icon PDF icon Innovative System-Level Design Environment Based on FORM for Transport Processing System [p 883]
Hollstein, T.
Abstract icon PDF icon From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Höreth, S.
Abstract icon PDF icon Dynamic Minimization of Word-Level Decision Diagrams [p 612]
Horneber, E.-H.
Abstract icon PDF icon EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
Hsiao, M.S.
Abstract icon PDF icon State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits [p 577]
Hsieh, Y.-W.
Abstract icon PDF icon Model Abstraction for Formal Verification [p 140]
Huertas, J.L.
Abstract icon PDF icon Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
Abstract icon PDF icon A Dynamic Model for the State Assignment Problem [p 835]
Abstract icon PDF icon An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Huss, S.A.
Abstract icon PDF icon A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks [p 721]
Hwang, S.H.
Abstract icon PDF icon Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]

I

Iglesias, C.A.
Abstract icon PDF icon A Knowledge-Based System for Hardware-Software Partitioning [p 914]
Inoue, A.
Abstract icon PDF icon Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Ishihara, T.
Abstract icon PDF icon Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Iyenaga, N.
Abstract icon PDF icon A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator [p 951]
Izaguirre, I.
Abstract icon PDF icon VHDL Teamwork, Organization Units and Workspace Management [p 297]

J

Jemai, A.
Abstract icon PDF icon Architectural Simulation in the Context of Behavioral Synthesis [p 590]
Jerraya, A.A.
Abstract icon PDF icon Architectural Simulation in the Context of Behavioral Synthesis [p 590]
Jess, J.A.G.
Abstract icon PDF icon Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
Abstract icon PDF icon A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Jha, N.K.
Abstract icon PDF icon CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]
Abstract icon PDF icon IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
Jiang, Y.-M.
Abstract icon PDF icon Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits [p 698]
Jiménez, C.J.
Abstract icon PDF icon XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Jochens, G.
Abstract icon PDF icon Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Johannes, F.M.
Abstract icon PDF icon Technology Mapping for Minimizing Gate and Routing Area [p 664]
Jürgensen, H.
Abstract icon PDF icon Built-In Self-Test with an Alternating Output [p 180]

K

Kahng, A.B.
Abstract icon PDF icon Interconnect Tuning Strategies for High-Performance ICs [p 471]
Kamon, M.
Abstract icon PDF icon An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
Kapur, N.
Abstract icon PDF icon Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Kassab, M.
Abstract icon PDF icon Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Kaul, M.
Abstract icon PDF icon Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures [p 389]
Kayss, M.
Abstract icon PDF icon From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Kazmierski, T.
Abstract icon PDF icon A Formal Description of VHDL-AMS Analogue Systems [p 916]
Abstract icon PDF icon Fuzzy-Logic Digital-Analogue Interfaces for Accurate Mixed-Signal Simulation [p 941]
Keding, H.
Abstract icon PDF icon FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Khare, J.
Abstract icon PDF icon Design-Manufacturing Interface: Part I -- Vision [p 550]
Abstract icon PDF icon Design-Manufacturing Interface: Part II -- Applications [p 557]
Khouri, K.S.
Abstract icon PDF icon IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
Kick, B.
Abstract icon PDF icon A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Kimura, H.
Abstract icon PDF icon A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator [p 951]
Kission, P.
Abstract icon PDF icon Architectural Simulation in the Context of Behavioral Synthesis [p 590]
Kitamura, F.
Abstract icon PDF icon PASTEL: A Parameterized Memory Characterization System [p 15]
Kleine, U.
Abstract icon PDF icon Automatic Topology Optimization for Analog Module Generators [p 961]
Knudsen, P.V.
Abstract icon PDF icon Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
Koegst, M.
Abstract icon PDF icon A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
Koehl, J.
Abstract icon PDF icon A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Kohno, M.
Abstract icon PDF icon PASTEL: A Parameterized Memory Characterization System [p 15]
Kolsteren, M.A.J.
Abstract icon PDF icon An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
Koufopavlou, O.
Abstract icon PDF icon Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Kovac, M.
Abstract icon PDF icon Universal Strong Encryption FPGA Core Implementation [p 923]
Kress, R.
Abstract icon PDF icon A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
Krodel, T.
Abstract icon PDF icon Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Kropf, T.
Abstract icon PDF icon Formal Specification in VHDL for Hardware Verification [p 257]
Kruse, L.
Abstract icon PDF icon Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Kuchcinski, K.
Abstract icon PDF icon Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Kücükcakar, K.
Abstract icon PDF icon Architectural Rule Checking for High-Level Synthesis [p 949]
Kuh, E.S.
Abstract icon PDF icon A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction [p 466]
Kukimoto, Y.
Abstract icon PDF icon Combinational Verification Based on High-Level Functional Specifications [p 803]
Kumar, A.
Abstract icon PDF icon Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
Kunzmann, A.
Abstract icon PDF icon Verification by Simulation Comparison Using Interface Synthesis [p 436]
Kurdahi, F.J.
Abstract icon PDF icon Layout-Driven High Level Synthesis for FPGA Based Architectures [p 446]
Kyung, C.-M.
Abstract icon PDF icon Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]

L

Lachowicz, S.W.
Abstract icon PDF icon Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Lago, E.
Abstract icon PDF icon XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Lakshminarayana, G.
Abstract icon PDF icon IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
Lee, M.T.-C.
Abstract icon PDF icon Functional Scan Chain Testing [p 278]
Leijten, J.A.J.
Abstract icon PDF icon Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
Leupers, R.
Abstract icon PDF icon Register-Constrained Address Computation in DSP Programs [p 929]
Levitan, S.P.
Abstract icon PDF icon Model Abstraction for Formal Verification [p 140]
Leyn, F.
Abstract icon PDF icon Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Li, J.
Abstract icon PDF icon An Algorithm to Determine Mutually Exclusive Operations in Behavioral Descriptions [p 457]
Lin, B.
Abstract icon PDF icon Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling [p 211]
Abstract icon PDF icon Efficient Verification Using Generalized Partial Order Analysis [p 782]
Lindenkreuz, T.
Abstract icon PDF icon Path Verification Using Boolean Satisfiability [p 965]
Lindermeir, W.M.
Abstract icon PDF icon Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
López, D.R.
Abstract icon PDF icon XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
López, J.C.
Abstract icon PDF icon A Knowledge-Based System for Hardware-Software Partitioning [p 914]
López, M.L.
Abstract icon PDF icon A Knowledge-Based System for Hardware-Software Partitioning [p 914]
Lorenz, G.
Abstract icon PDF icon A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Lu, A.
Abstract icon PDF icon Technology Mapping for Minimizing Gate and Routing Area [p 664]
Lubaszewski, M.
Abstract icon PDF icon Microsystems Testing: An Approach and Open Problems [p 524]
Ludwig, T.
Abstract icon PDF icon A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]

M

Macii, E.
Abstract icon PDF icon Power Estimation of Behavioral Descriptions [p 762]
Abstract icon PDF icon Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Madsen, J.
Abstract icon PDF icon Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
Maestro, J.A.
Abstract icon PDF icon A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
Maheshwari, N.
Abstract icon PDF icon Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
Maly, W.
Abstract icon PDF icon Design-Manufacturing Interface: Part I -- Vision [p 550]
Abstract icon PDF icon Design-Manufacturing Interface: Part II -- Applications [p 557]
Abstract icon PDF icon Performance-Manufacturability Tradeoffs in IC Design [p 563]
Manhaeve, H.
Abstract icon PDF icon A Fully Digital Controlled Off-Chip IDDQ Measurement Unit [p 495]
Abstract icon PDF icon IOCIMU -- An Integrated Off-Chip IDDQMeasurement Unit [p 959]
Marculescu, D.
Abstract icon PDF icon Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
Marculescu, R.
Abstract icon PDF icon Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
Marek-Sadowska, M.
Abstract icon PDF icon Functional Scan Chain Testing [p 278]
Marques, N.
Abstract icon PDF icon An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
Martin, G.
Abstract icon PDF icon Design Methodologies for System Level IP [p 286]
Martin, H.-G.
Abstract icon PDF icon A Comparing Study of Technology Mapping for FPGA [p 939]
Martínez, M.
Abstract icon PDF icon A Dynamic Model for the State Assignment Problem [p 835]
Marwedel, P.
Abstract icon PDF icon Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems [p 912]
Abstract icon PDF icon Register-Constrained Address Computation in DSP Programs [p 929]
Mecha, H.
Abstract icon PDF icon A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
Menchikov, A.
Abstract icon PDF icon High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Mendías, J.M.
Abstract icon PDF icon Correct High-Level Synthesis: A Formal Perspective [p 977]
Mesman, B.
Abstract icon PDF icon A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Metra, C.
Abstract icon PDF icon Novel Technique for Testing FPGAs [p 89]
Abstract icon PDF icon Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
Meyr, H.
Abstract icon PDF icon FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Mir, S.
Abstract icon PDF icon Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
Mittwollen, N.
Abstract icon PDF icon VHDL-AMS: The Missing Link in System Design -- Experiments with Unified Modelling in Automotive Engineering [p 59]
Mojoli, G.
Abstract icon PDF icon Novel Technique for Testing FPGAs [p 89]
Monjau, D.
Abstract icon PDF icon An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Montiel-Nelson, J.A.
Abstract icon PDF icon A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
Moser, E.
Abstract icon PDF icon VHDL-AMS: The Missing Link in System Design -- Experiments with Unified Modelling in Automotive Engineering [p 59]
Mozos, D.
Abstract icon PDF icon A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
Mrva, M.
Abstract icon PDF icon Enhanced Reuse and Teamwork Capabilities for an Object-Oriented Extension of VHDL [p 250]
Abstract icon PDF icon A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
Muddu, S.
Abstract icon PDF icon Interconnect Tuning Strategies for High-Performance ICs [p 471]
Müller, A.
Abstract icon PDF icon A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
Muller, F.
Abstract icon PDF icon A Programmable Multi-Language Generator for CoDesign [p 927]
Müller-Glaser, K.D.
Abstract icon PDF icon Advanced Optimistic Approaches in Logic Simulation [p 362]
Müller-Wipperfürth, T.
Abstract icon PDF icon Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base [p 931]
Münch, M.
Abstract icon PDF icon Generation of Interconnect Topologies for Communication Synthesis [p 36]
Mutz, M.
Abstract icon PDF icon Register Transfer Level VHDL Models without Clocks [p 153]

N

Nag, P.K.
Abstract icon PDF icon Design-Manufacturing Interface: Part I -- Vision [p 550]
Abstract icon PDF icon Design-Manufacturing Interface: Part II -- Applications [p 557]
Nagoya, A.
Abstract icon PDF icon Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
Naroska, E.
Abstract icon PDF icon Parallel VHDL Simulation [p 159]
Navarro, D.
Abstract icon PDF icon VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
Nebel, W.
Abstract icon PDF icon Object-Oriented Modelling of Parallel Hardware Systems [p 234]
Abstract icon PDF icon A Flexible Message Passing Mechanism for Objective VHDL [p 242]
Abstract icon PDF icon Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Neul, R.
Abstract icon PDF icon A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Nicolaidis, M.
Abstract icon PDF icon Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]
Abstract icon PDF icon Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
Nicolau, A.
Abstract icon PDF icon Data Cache Sizing for Embedded Processor Applications [p 925]
Nicoli, F.
Abstract icon PDF icon Denotational Semantics of a Behavioral Subset of VHDL [p 975]
Niemann, R.
Abstract icon PDF icon Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems [p 912]
Niggemeyer, D.
Abstract icon PDF icon Core Interconnect Testing Hazards [p 953]
Nikolaidis, S.
Abstract icon PDF icon Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]
Abstract icon PDF icon Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Nordholz, P.
Abstract icon PDF icon Core Interconnect Testing Hazards [p 953]
Nourani, M.
Abstract icon PDF icon A Bypass Scheme for Core-Based System Fault Testing [p 979]
Núnez, A.
Abstract icon PDF icon A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]

O

Öberg, J.
Abstract icon PDF icon Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
Ogawa, K.
Abstract icon PDF icon PASTEL: A Parameterized Memory Characterization System [p 15]
Oh, J.
Abstract icon PDF icon Gated Clock Routing Minimizing the Switched Capacitance [p 692]
Olcoz, S.
Abstract icon PDF icon VHDL Teamwork, Organization Units and Workspace Management [p 297]
Abstract icon PDF icon Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Orailoglu, A.
Abstract icon PDF icon Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
Ottaviano, E.
Abstract icon PDF icon Temperature Effect on Delay for Low Voltage Applications [p 680]
Otten, R.H.J.M.
Abstract icon PDF icon Constraints Space Management for the Layout of Analog IC's [p 971]
Otterstedt, J.
Abstract icon PDF icon Core Interconnect Testing Hazards [p 953]
Ouyang, C.
Abstract icon PDF icon Design-Manufacturing Interface: Part II -- Applications [p 557]
Page, I.
Abstract icon PDF icon Design of Future Systems [p 343]

P

Panda, P.R.
Abstract icon PDF icon Data Cache Sizing for Embedded Processor Applications [p 925]
Panda, R.
Abstract icon PDF icon CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Papachristou, C.
Abstract icon PDF icon Testing DSP Cores Based on Self-Test Programs [p 166]
Abstract icon PDF icon A Bypass Scheme for Core-Based System Fault Testing [p 979]
Papakonstantinou, G.
Abstract icon PDF icon AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]
Park, I.-C.
Abstract icon PDF icon Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
Parulkar, I.
Abstract icon PDF icon Scheduling and Module Assignment for Reducing BIST Resources [p 66]
Pasquier, O.
Abstract icon PDF icon A Programmable Multi-Language Generator for CoDesign [p 927]
Pastor, E.
Abstract icon PDF icon Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
Pastore, S.
Abstract icon PDF icon Novel Technique for Testing FPGAs [p 89]
Pedram, M.
Abstract icon PDF icon Gated Clock Routing Minimizing the Switched Capacitance [p 692]
Abstract icon PDF icon Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
Penalba, O.
Abstract icon PDF icon VHDL Teamwork, Organization Units and Workspace Management [p 297]
Peng, Z.
Abstract icon PDF icon An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis [p 74]
Abstract icon PDF icon Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Peralías, E.
Abstract icon PDF icon An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Pflueger, T.
Abstract icon PDF icon A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Pires, R.
Abstract icon PDF icon Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Piuri, V.
Abstract icon PDF icon A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
Plaza, P.
Abstract icon PDF icon ATM Traffic Shaper: ATS [p 96]
Pomeranz, I.
Abstract icon PDF icon Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
Abstract icon PDF icon A Synthesis Procedure for Flexible Logic Functions [p 973]
Abstract icon PDF icon Design-for-Testability for Synchronous Sequential Circuits Using Locally Available Lines [p 983]
Poncino, M.
Abstract icon PDF icon Power Estimation of Behavioral Descriptions [p 762]
Pop, P.
Abstract icon PDF icon Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Portal, J.M.
Abstract icon PDF icon RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
Post, G.
Abstract icon PDF icon A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
Prieto, J.A.
Abstract icon PDF icon An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Prihozhy, A.
Abstract icon PDF icon Asynchronous Scheduling and Allocation [p 963]
Prinetto, P.
Abstract icon PDF icon Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Abstract icon PDF icon Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Pullela, S.
Abstract icon PDF icon CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Putzke-Röming, W.
Abstract icon PDF icon A Flexible Message Passing Mechanism for Objective VHDL [p 242]
Pyttel, A.
Abstract icon PDF icon PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]

Q

Quintana, J.M.
Abstract icon PDF icon A Dynamic Model for the State Assignment Problem [p 835]

R

Rabaey, J.
Abstract icon PDF icon An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
Rabe, D.
Abstract icon PDF icon Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Radetzki, M.
Abstract icon PDF icon A Flexible Message Passing Mechanism for Objective VHDL [p 242]
Radhakrishnan, S.
Abstract icon PDF icon Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
Rassau, A.M.
Abstract icon PDF icon Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Reddy, S.M.
Abstract icon PDF icon Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
Abstract icon PDF icon A Synthesis Procedure for Flexible Logic Functions [p 973]
Abstract icon PDF icon Design-for-Testability for Synchronous Sequential Circuits Using Locally Available Lines [p 983]
Reetz, R.
Abstract icon PDF icon Formal Specification in VHDL for Hardware Verification [p 257]
Rencz, M.
Abstract icon PDF icon Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]
Renovell, M.
Abstract icon PDF icon RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
Abstract icon PDF icon Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]
Ribas-Xirgo, L.
Abstract icon PDF icon On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits [p 624]
Ricco, B.
Abstract icon PDF icon Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
Richardson, A.M.D.
Abstract icon PDF icon An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Riesgo, T.
Abstract icon PDF icon Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
Ringe, M.
Abstract icon PDF icon Path Verification Using Boolean Satisfiability [p 965]
Robins, G.
Abstract icon PDF icon Improved Approximation Bounds for the Group Steiner Problem [p 406]
Rodríguez-Montanés, R.
Abstract icon PDF icon Estimation of the Defective IDDQCaused by Shorts in Deep-Submicron CMOS ICs [p 490]
Roethig, W.
Abstract icon PDF icon Power and Timing Modeling for ASIC Designs [p 969]
Rosenberger, R.
Abstract icon PDF icon A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks [p 721]
Rosenstiel, W.
Abstract icon PDF icon A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment [p 226]
Abstract icon PDF icon Formal Verification: A New Standard CAD Tool for the Industrial Design Flow [p 422]
Abstract icon PDF icon Verification by Simulation Comparison Using Interface Synthesis [p 436]
Abstract icon PDF icon Cross-Level Hierarchical High-Level Synthesis [p 451]
Abstract icon PDF icon Next Generation System Level Design Tools [p 488]
Abstract icon PDF icon A Comparing Study of Technology Mapping for FPGA [p 939]
Rouzeyre, B.
Abstract icon PDF icon Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Roy, S.
Abstract icon PDF icon PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
Rozon, C.
Abstract icon PDF icon VHDL Modelling and Analysis of Fault Secure Systems [p 148]
Rudnick, E.M.
Abstract icon PDF icon Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Rueda, A.
Abstract icon PDF icon Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
Abstract icon PDF icon An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Runje, D.
Abstract icon PDF icon Universal Strong Encryption FPGA Core Implementation [p 923]
Rutten, J.W.J.M.
Abstract icon PDF icon An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]

S

Sakallah, K.A.
Abstract icon PDF icon AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
Salapura, V.
Abstract icon PDF icon Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
Salice, F.
Abstract icon PDF icon A Model for System-Level Timed Analysis and Profiling [p 204]
Abstract icon PDF icon Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
Salvi, D.
Abstract icon PDF icon Novel Technique for Testing FPGAs [p 89]
Sami, M.
Abstract icon PDF icon A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
Sánchez-Solano, S.
Abstract icon PDF icon XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Sansen, W.
Abstract icon PDF icon Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Sapatnekar, S.S.
Abstract icon PDF icon Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
Sarmiento, R.
Abstract icon PDF icon A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
Sarto, E.
Abstract icon PDF icon Interconnect Tuning Strategies for High-Performance ICs [p 471]
Sawada, H.
Abstract icon PDF icon Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
Scheible, J.
Abstract icon PDF icon An Interactive Router for Analog IC Design [p 414]
Schietke, J.
Abstract icon PDF icon Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset [p 325]
Schmerler, S.
Abstract icon PDF icon Advanced Optimistic Approaches in Logic Simulation [p 362]
Schneider, C.
Abstract icon PDF icon From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Schneider, K.
Abstract icon PDF icon Formal Specification in VHDL for Hardware Verification [p 257]
Scholl, C.
Abstract icon PDF icon Multi-Output Functional Decomposition with Exploitation of Don't Cares [p 743]
Schulze, S.
Abstract icon PDF icon An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Schumacher, G.
Abstract icon PDF icon Object-Oriented Modelling of Parallel Hardware Systems [p 234]
Schwarz, P.
Abstract icon PDF icon A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Sciuto, D.
Abstract icon PDF icon A Model for System-Level Timed Analysis and Profiling [p 204]
Abstract icon PDF icon Power Estimation of Behavioral Descriptions [p 762]
Abstract icon PDF icon Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Abstract icon PDF icon Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
Sechi, G.
Abstract icon PDF icon Novel Technique for Testing FPGAs [p 89]
Sedlmeier, A.
Abstract icon PDF icon PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
Shao, J.
Abstract icon PDF icon MCM Interconnect Design Using Two-Pole Approximation [p 544]
Sharma, R.
Abstract icon PDF icon Interconnect Tuning Strategies for High-Performance ICs [p 471]
Shen, Z.
Abstract icon PDF icon An Effective General Connectivity Concept for Clustering [p 398]
Shi, C.-J.R.
Abstract icon PDF icon Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
Shields Neely, W.
Abstract icon PDF icon Reconfigurable Logic for Systems on a Chip [p 340]
Shirakawa, K.
Abstract icon PDF icon Innovative System-Level Design Environment Based on FORM for Transport Processing System [p 883]
Silvano, C.
Abstract icon PDF icon Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Silveira, L.M.
Abstract icon PDF icon An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
Abstract icon PDF icon Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
Simon, P.
Abstract icon PDF icon Design-Manufacturing Interface: Part II -- Applications [p 557]
Song, J.
Abstract icon PDF icon An Effective General Connectivity Concept for Clustering [p 398]
Sonza Reorda, M.
Abstract icon PDF icon Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Abstract icon PDF icon Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Srinivasan, V.
Abstract icon PDF icon Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
Stenz, G.
Abstract icon PDF icon Technology Mapping for Minimizing Gate and Routing Area [p 664]
Straka, B.
Abstract icon PDF icon A Fully Digital Controlled Off-Chip IDDQ Measurement Unit [p 495]
Abstract icon PDF icon IOCIMU -- An Integrated Off-Chip IDDQMeasurement Unit [p 959]
Strik, M.
Abstract icon PDF icon A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Sung, W.
Abstract icon PDF icon Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
Svajda, M.
Abstract icon PDF icon A Fully Digital Controlled Off-Chip IDDQ Measurement Unit [p 495]
Abstract icon PDF icon IOCIMU -- An Integrated Off-Chip IDDQMeasurement Unit [p 959]
Székely, V.
Abstract icon PDF icon Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]

T

Tan, S.-Y.
Abstract icon PDF icon The Design of an Asynchronous VHDL Synthesizer [p 44]
Tanurhan, Y.
Abstract icon PDF icon Advanced Optimistic Approaches in Logic Simulation [p 362]
Thole, M.
Abstract icon PDF icon EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
Tian, M.W.
Abstract icon PDF icon Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
Timmer, A.H.
Abstract icon PDF icon Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
Abstract icon PDF icon A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Tlili, I.B.S.
Abstract icon PDF icon March Tests for Word-Oriented Memories [p 501]
Tomiyama, H.
Abstract icon PDF icon Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Torroja, Y.
Abstract icon PDF icon Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
Treytnar, D.
Abstract icon PDF icon Core Interconnect Testing Hazards [p 953]
Tsanakas, P.
Abstract icon PDF icon AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]

U

Uceda, J.
Abstract icon PDF icon Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
Urriza, I.
Abstract icon PDF icon VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]

V

van de Goor, A.J.
Abstract icon PDF icon March Tests for Word-Oriented Memories [p 501]
van Eijk, C.A.J.
Abstract icon PDF icon Sequential Equivalence Checking without State Space Traversal [p 618]
Abstract icon PDF icon An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
van Meerbergen, J.L.
Abstract icon PDF icon Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
Abstract icon PDF icon A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Vandenbussche, J.
Abstract icon PDF icon Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Vanneuville, J.
Abstract icon PDF icon A Fully Digital Controlled Off-Chip IDDQMeasurement Unit [p 495]
Vázquez, D.
Abstract icon PDF icon Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
Veith, C.
Abstract icon PDF icon PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
Velasco-Medina, J.
Abstract icon PDF icon Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
Vemuri, R.
Abstract icon PDF icon Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
Abstract icon PDF icon Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures [p 389]
Vercauteren, S.
Abstract icon PDF icon Efficient Verification Using Generalized Partial Order Analysis [p 782]
Verkest, D.
Abstract icon PDF icon Efficient Verification Using Generalized Partial Order Analysis [p 782]
Vietti, R.
Abstract icon PDF icon Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Vijayan, G.
Abstract icon PDF icon CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Violante, M.
Abstract icon PDF icon Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Vogels, T.J.
Abstract icon PDF icon Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
Völkel, H.
Abstract icon PDF icon A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor [p 937]
Volpe, L.
Abstract icon PDF icon Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Vrudhula, S.B.K.
Abstract icon PDF icon Data Driven Power Optimization of Sequential Circuits [p 686]
Vygen, J.
Abstract icon PDF icon Algorithms for Detailed Placement of Standard Cells [p 321]

W

Wahl, M.
Abstract icon PDF icon A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
Abstract icon PDF icon A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor [p 937]
Waldschmidt, K.
Abstract icon PDF icon Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
Wan, M.
Abstract icon PDF icon An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
Wang, D.
Abstract icon PDF icon A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction [p 466]
Wang, L.-C.
Abstract icon PDF icon Measuring the Effectiveness of Various Design Validation Approaches for PowerPCTMMicroprocessor Arrays [p 273]
Wang, Q.
Abstract icon PDF icon Data Driven Power Optimization of Sequential Circuits [p 686]
Wehn, N.
Abstract icon PDF icon Embedded DRAM Architectural Trade-Offs [p 704]
White, J.
Abstract icon PDF icon An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
Whittemore, J.P.
Abstract icon PDF icon AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
Wilkinson, T.D.
Abstract icon PDF icon Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Willems, M.
Abstract icon PDF icon FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Williams, T.W.
Abstract icon PDF icon Core Interconnect Testing Hazards [p 953]
Wolf, M.
Abstract icon PDF icon Automatic Topology Optimization for Analog Module Generators [p 961]
Wong, D.F.
Abstract icon PDF icon A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing [p 479]
Wunderlich, H.-J.
Abstract icon PDF icon Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
Wünsche, S.
Abstract icon PDF icon A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]

X

Xu, M.
Abstract icon PDF icon Layout-Driven High Level Synthesis for FPGA Based Architectures [p 446]

Y

Yamashita, S.
Abstract icon PDF icon Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
Yang, T.
Abstract icon PDF icon An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis [p 74]
Yarmolik, V.N.
Abstract icon PDF icon Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
Yasuura, H.
Abstract icon PDF icon Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Yeh, C.-W.
Abstract icon PDF icon On Removing Multiple Redundancies in Combinational Circuits [p 738]
Yen, W.-F.
Abstract icon PDF icon The Design of an Asynchronous VHDL Synthesizer [p 44]
Yi, J.-H.
Abstract icon PDF icon Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
Yu, T.C.B.
Abstract icon PDF icon Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

Z

Zarkesh, A.M.
Abstract icon PDF icon Power and Timing Modeling for ASIC Designs [p 969]
Zelikovsky, A.
Abstract icon PDF icon Improved Approximation Bounds for the Group Steiner Problem [p 406]
Zeng, J.
Abstract icon PDF icon Measuring the Effectiveness of Various Design Validation Approaches for PowerPCTMMicroprocessor Arrays [p 273]
Zhao, W.
Abstract icon PDF icon Testing DSP Cores Based on Self-Test Programs [p 166]
Zhuang, W.
Abstract icon PDF icon An Effective General Connectivity Concept for Clustering [p 398]
Zorian, Y.
Abstract icon PDF icon RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
Abstract icon PDF icon Built-In Self-Test with an Alternating Output [p 180]