DATE 1998 Session Index
Session 1A: Design Optimization of Building Blocks
Session 1B: HW/SW Partitioning and Communication Synthesis
Session 1C: Asynchronous and Hybrid VHDL-Based Design
Session 1D: Data Path and FPGA Testing
Session 2A: Design Methods for High Performance Applications
Session 2B: Scheduling in Embedded Systems
Session 2C: Advanced Techniques for VHDL Design
Session 2D: Novel BIST Approaches
Session 3A: Architectures for Image Processing
Session 3B: Scheduling and Analysis of HW/SW Systems
Session 3C: Extensions to VHDL
Session 3D: Error Detection and Design Validation
Session 3E: Hot Topic: IP Based System-on-a-Chip Design
Session 4A: Design Reuse Methodologies
Session 4B: Flat and Timing-Driven Processor Design
Session 4C: Hot Topic: Reconfigurable Systems
Session 4D: Digital Simulation and Estimation
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures
Session 5B: Partitioning and Routing
Session 5C: Panel -- Formal Verification: A New Standard CAD Tool for the Industrial Design Flow
Session 5D: Simulation for High-Level Design
Session 6A: Architectural Synthesis
Session 6B: Timing and Crosstalk in Interconnect
Session 6C: Panel: Next Generation System Design Tools
Session 6D: IDDQ and Memory Testing
Session 7A: Microsystems
Session 7B: Interconnect Modeling
Session 7C: Design for Manufacturability -- Embedded Tutorial
Session 7D: Sequential Circuit Testing
Session 8A: Issues in Behavioral Synthesis
Session 8B: Formal Equivalence Checking Using Decision Diagrams
Session 8C: Hot Topic: Silicon Debug of Systems-on-Chips
Session 8D: Characterization and Verification of Analogue Circuits
Session 9A: Benchmark Circuits, Technology Mapping and Scan Chains
Session 9B: Physical to Gate Level Design for Low-Power
Session 9C: Hot Topic: Embedded Memory and Embedded Logic
Session 9D: Analogue Circuit Modeling and Design Methodology
Session 10A: Combinational Logical Synthesis
Session 10B: High Level Power Estimation
Session 10C: Petri Nets and Dedicated Formalisms
Session 10D: Mixed-Signal Test and DFT
Session 11A: Sequential Logic Synthesis
Session 11B: High-Level Power Optimization
Session 11C: System Architecture Design
Session 11D: Simulation and Test Tools for Analogue Circuits
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