Event Steering Board

Conference Organizing Committe

Programme Topic Chairs

Vendors Committee

Technical Programme Committee

Welcome to DATE 98

Keynote Addresses Summaries

Tutorials

List of Reviewers

Moderators: *Y. Zorian, LogicVision, USA, P. Plaza, Telefonca I+D, Spain*

- Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]
*A. Chatzigeorgiou and S. Nikolaidis*- Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]
*M. Nicolaidis and R.O. Duarte*- PASTEL: A Parameterized Memory Characterization System [p 15]
*K. Ogawa, M. Kohno, and F. Kitamura*

Moderators: *K. Buchenrieder, Siemens AG, Germany, A. Jerraya, TIMA, Grenoble, France*

- Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
*J. Grode, P.V. Knudsen, and J. Madsen*- Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
*V. Srinivasan, S. Radhakrishnan, and R. Vemuri*- Generation of Interconnect Topologies for Communication Synthesis [p 36]
*M. Gasteier, M. Münch, and M. Glesner*

Moderators: *A. Vachoux, Ecole Polytechnique Federale de Lausanne, Switzerland, T. Kazmierski, University of Southampton, UK *

- The Design of an Asynchronous VHDL Synthesizer [p 44]
*S.-Y. Tan, S.B. Furber, and W.-F. Yen*- Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
*C. Grimm and K. Waldschmidt*- VHDL-AMS: The Missing Link in System Design -- Experiments with Unified Modelling in Automotive Engineering [p 59]
*E. Moser and N. Mittwollen*

Moderators: * H.-J. Wunderlich, University of Stuttgart, Germany, M. Nicolaidis, TIMA, Grenoble, France*

- Scheduling and Module Assignment for Reducing BIST Resources [p 66]
*I. Parulkar, S.K. Gupta, and M.A. Breuer*- An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis [p 74]
*T. Yang and Z. Peng*- RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
*M. Renovell, J.M. Portal, J. Figueras, and Y. Zorian*- Novel Technique for Testing FPGAs [p 89]
*C. Metra, G. Mojoli, S. Pastore, D. Salvi, and G. Sechi*

Moderators: *Y. Torroja, Polytechnical University of Madrid, Spain, R. Sarmiento, University of Las Palmas de Gran Canaria, Spain *

- ATM Traffic Shaper: ATS [p 96]
*J.C. Diaz, P. Plaza, and J. Crespo*- XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
*E. Lago, C.J. Jiménez, D.R. López, S. Sánchez-Solano, and A. Barriga*- High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
*W. Eppler, T. Fischer, H. Gemmeke, and A. Menchikov*

Moderators: * S.A. Huss, Darmstadt University of Technology, Germany, H.-P. Amann, University of Neuchatel, Switzerland*

- CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]
*B.P. Dave and N.K. Jha*- Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
*J.A.J. Leijten, J.L. van Meerbergen, A.H. Timmer, and J.A.G. Jess*- Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
*P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, and P. Pop*

Moderators: *E. Villar, University of Cantabria, Spain, D. Sciuto, Politecnico di Milano, Italy*

- Model Abstraction for Formal Verification [p 140]
*Y.-W. Hsieh and S.P. Levitan*- VHDL Modelling and Analysis of Fault Secure Systems [p 148]
*J. Coppens, D. Al-Khalili, and C. Rozon*- Register Transfer Level VHDL Models without Clocks [p 153]
*M. Mutz*- Parallel VHDL Simulation [p 159]
*E. Naroska*

Moderators: *E. Aas, Norwegian University of Science and Technology, Norway, Z. Peng, Linköping University, Sweden*

- Testing DSP Cores Based on Self-Test Programs [p 166]
*W. Zhao and C. Papachristou*- Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
*V.N. Yarmolik, S. Hellebrand, and H.-J. Wunderlich*- Built-In Self-Test with an Alternating Output [p 180]
*T. Bogue, M. Gössel, H. Jürgensen, and Y. Zorian*

Moderators: *I. Bolsens, IMEC, Belgium, A. Nunez, University of Las Palmas de Gran Canaria, Spain*

- From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
*C. Schneider, M. Kayss, T. Hollstein, and J. Deicke*- Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
*A.M. Rassau, K. Eshraghian, H. Cheung, S.W. Lachowicz, T.C.B. Yu, W.A. Crossland, and T.D. Wilkinson*- VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
*I. Urriza, J.I. Artigas, J.I. García, L.A. Barragán, and D. Navarro*

Moderators: *R. Ernst, Technical University of Braunschweig, Germany, P. van der Wolf, Philips Research Laboratories, The Netherlands*

- A Model for System-Level Timed Analysis and Profiling [p 204]
*A. Allara, W. Fornaciari, F. Salice, and D. Sciuto*- Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling [p 211]
*B. Lin*- A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
*J.A. Maestro, D. Mozos, and H. Mecha*- A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment [p 226]
*J. Gerlach and W. Rosenstiel*

Moderators: *S. Maginot, LEDA, France, W. Ecker, Siemens AG, Germany*

- Object-Oriented Modelling of Parallel Hardware Systems [p 234]
*G. Schumacher and W. Nebel*- A Flexible Message Passing Mechanism for Objective VHDL [p 242]
*W. Putzke-Röming, M. Radetzki, and W. Nebel*- Enhanced Reuse and Teamwork Capabilities for an Object-Oriented Extension of VHDL [p 250]
*M. Mrva*- Formal Specification in VHDL for Hardware Verification [p 257]
*R. Reetz, K. Schneider, and T. Kropf*

Moderators: *T. Vierhaus, Technical University of Cottbus, Germany, R. Segers, Philips Semiconductors, The Netherlands*

- A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
*A. Antola, V. Piuri, and M. Sami*- Measuring the Effectiveness of Various Design Validation Approaches for PowerPC
^{TM}Microprocessor Arrays [p 273] *L.-C. Wang, M.S. Abadir, and J. Zeng*- Functional Scan Chain Testing [p 278]
*D. Chang, M.T.-C. Lee, K.-T. Cheng, and M. Marek-Sadowska*

Co-ordinators: *Carlo Guardiani, SGS-Thomson, Italy Wolfgang Nebel, Oldenburg University and OFFIS, Germany*

Moderator: *Alberto Sangiovanni-Vincentelli, University of California at Berkeley, USA*

Speakers: *Grant Martin, Cadence, USA Mike Muller, ARM, UK Bart De Loore, Philips Semiconductors, The Netherlands*

Panelists: *Doug Fairbairn, VSI Alliance, USA Pietro Erratico, SGS-Thomson, Italy Faysal Soheil, Synopsys, USA *

- Design Methodologies for System Level IP [p 286]
*G. Martin*- IP-Based System-on-a-Chip Design [p 290]
*B. De Loore*

Moderators: *J. Heaton, ICL, UK, R. Seepold, FZI Karlsruhe, Germany*

- A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
*M. Koegst, P. Conradi, D. Garte, and M. Wahl*- VHDL Teamwork, Organization Units and Workspace Management [p 297]
*S. Olcoz, L. Ayuda, I. Izaguirre, and O. Penalba*- An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
*J. Böttger, K. Agsteiner, D. Monjau, and S. Schulze*

Moderators: *E. Barke, University of Hannover, Germany, I. Rugen-Herzig, Temic Telefunken Microelectronic GmbH, Germany*

- A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
*J. Koehl, U. Baur, T. Ludwig, B. Kick, and T. Pflueger*- Algorithms for Detailed Placement of Standard Cells [p 321]
*J. Vygen*- Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset [p 325]
*U. Fassnacht and J. Schietke*- A Sequential Detailed Router for Huge Grid Graphs [p 332]
*A. Hetzel*

Co-ordinator: *Ivo Bolsens, IMEC, Belgium*

Moderator: *Nadir Bagherzadeh, University of California at Irvine, USA*

Speakers: *W. Shields Neely, National Semiconductor, USA Jan Rabaey, University of California at Berkeley, USA Ian Page, University of Oxford, UK *

- Reconfigurable Logic for Systems on a Chip [p 340]
*W. Shields Neely*- An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
*J. Rabaey and M. Wan*- Design of Future Systems [p 343]
*I. Page*

Moderators: *Peter Schwarz, Fraunhofer EAS Dresden, Germany, H. Fleurkens, Philips Research Laboratories, The Netherlands*

- AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
*V. Chandramouli, J.P. Whittemore, and K.A. Sakallah*- Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
*D. Rabe, G. Jochens, L. Kruse, and W. Nebel*- Advanced Optimistic Approaches in Logic Simulation [p 362]
*S. Schmerler, Y. Tanurhan, and K.D. Müller-Glaser*

Moderators: *F. Kurdahi, University of California, Irvine, USA, A. Jerraya, TIMA, Grenoble, France*

- PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
*A. Pyttel, A. Sedlmeier, and C. Veith*- A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
*B. Mesman, M. Strik, A.H. Timmer, J.L. van Meerbergen, and J.A.G.Jess*- Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
*J.-H. Yi, H. Choi, I.-C. Park, S.H. Hwang, and C.-M. Kyung*- Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures [p 389]
*M. Kaul and R. Vemuri*

Moderators: *M.D.F. Wong, University of Texas at Austin, USA, F.M. Johannes, Technical University of Munich, Germany*

- An Effective General Connectivity Concept for Clustering [p 398]
*J. Song, Z. Shen, and W. Zhuang*- Improved Approximation Bounds for the Group Steiner Problem [p 406]
*C.S. Helvig, G. Robins, and A. Zelikovsky*- An Interactive Router for Analog IC Design [p 414]
*T. Adler and J. Scheible*

Organizers: *Wolfgang Rosenstiel, University of Tübingen, Germany Gerry Musgrave, Brunel University, UK*

Moderator: *Gerry Musgrave, Brunel University, UK*

Panelists: *Dominique Borrione, TIMA-UJF, France Antun Domic, Synopsys, USA Ramayya Kumar, Verysys, Germany Alan Page, Abstract Design Automation, UK Michael Payer, Siemens, Germany *

Moderators: *J. Forrest, UMIST, Manchester, UK M. Pfaff, Johannes Kepler University Linz, Austria*

- A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
*G. Post, A. Müller, and T. Grötker*- FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
*H. Keding, M. Willems, M. Coors, and H. Meyr*- Verification by Simulation Comparison Using Interface Synthesis [p 436]
*C. Hansen, A. Kunzmann, and W. Rosenstiel*

Moderators: *P. Marwedel, University of Dortmund, Germany, A. Timmer, Philips Research Laboratories, The Netherlands*

- Layout-Driven High Level Synthesis for FPGA Based Architectures [p 446]
*M. Xu and F.J. Kurdahi*- Cross-Level Hierarchical High-Level Synthesis [p 451]
*O. Bringmann and W. Rosenstiel*- An Algorithm to Determine Mutually Exclusive Operations in Behavioral Descriptions [p 457]
*J. Li and R.K. Gupta*

Moderators: *R. Peset Llopis, Philips Research Laboratories, The Netherlands, B. Schürmann, University of Kaiserslautern, Germany*

- A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction [p 466]
*D. Wang and E.S. Kuh*- Interconnect Tuning Strategies for High-Performance ICs [p 471]
*A.B. Kahng, S. Muddu, E. Sarto, and R. Sharma*- A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing [p 479]
*C.C.N. Chu and D.F. Wong*

Co-ordinators: *Wolfgang Rosenstiel, University of Tübingen, Germany Joachim Kunkel, Synopsys, USA*

Moderator: *Joachim Kunkel, Synopsys, USA*

Panelists: *Misha Burich, Cadance/Alta, USA Raul Camposano, Synopsys, USA Mark Genoe, Alcatel, Belgium Lev Markov, Mentor Graphics, USA Steve Schulz, Texas Instruments, USA *

Moderators: *M. Sachdev, Philips Research Laboratories, The Netherlands, B. Straube, FhG IIS/EAS Dresden, Germany*

- Estimation of the Defective I
_{DDQ}Caused by Shorts in Deep-Submicron CMOS ICs [p 490] *R. Rodríguez-Montanés and J. Figueras*- A Fully Digital Controlled Off-Chip I
_{DDQ}Measurement Unit [p 495] *B. Straka, H. Manhaeve, J. Vanneuville, and M. Svajda*- March Tests for Word-Oriented Memories [p 501]
*A.J. van de Goor and I.B.S. Tlili*

Moderators: *J. Bausells, CNM, Barcelona, Spain, M. Glesner, Technical University of Darmstadt, Germany*

- A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
*R. Neul, U. Becker, G. Lorenz, P. Schwarz, J. Haase, and S. Wünsche*- Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]
*V. Székely and M. Rencz*- Microsystems Testing: An Approach and Open Problems [p 524]
*M. Lubaszewski, E.F. Cota, and B. Courtois*

Moderators: *F.M. Johannes, Technical University of Munich, Germany, J. Koehl, IBM Deutschland Entwicklung GmbH, Germany*

- Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Padé Approximation [p 530]
*R.W. Freund and P. Feldmann*- An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
*N. Marques, M. Kamon, J. White, and L.M. Silveira*- MCM Interconnect Design Using Two-Pole Approximation [p 544]
*J. Shao and R.M.M. Chen*

Moderators: *M. Servit, Czech Technical University, Czech Republic, R. Peset Llopis, Philips Research Laboratories, The Netherlands*

- Design-Manufacturing Interface: Part I -- Vision [p 550]
*W. Maly, H.T. Heineken, J. Khare, and P.K. Nag*- Design-Manufacturing Interface: Part II -- Applications [p 557]
*W. Maly, H.T. Heineken, J. Khare, P.K. Nag, P. Simon, and C. Ouyang*- Performance-Manufacturability Tradeoffs in IC Design [p 563]
*H.T. Heineken and W. Maly*

Moderators: * C. Landrault, LIRMM, France, D. Medina, Italtel, Italy*

- Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
*E.M. Rudnick, R. Vietti, A. Ellis, F. Corno, P. Prinetto, and M. Sonza Reorda*- State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits [p 577]
*M.S. Hsiao and S.T. Chakradhar*- Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
*R. Guo, I. Pomeranz, and S.M. Reddy*

Moderators: *J. van Meerbergen, Philips Research Laboratories, The Netherlands, H. Hermanani, Lebanese American University, Lebanon*

- Architectural Simulation in the Context of Behavioral Synthesis [p 590]
*A. Jemai, P. Kission, and A.A. Jerraya*- Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
*J. Öberg, A. Kumar, and A. Hemani*- Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
*S.N. Hamilton and A. Orailoglu*

Moderators: *T. Filkorn, Siemens AG, Germany, H. Eveking, Darmstadt University of Technology, Germany*

- Dynamic Minimization of Word-Level Decision Diagrams [p 612]
*S. Höreth and R. Drechsler*- Sequential Equivalence Checking without State Space Traversal [p 618]
*C.A.J. van Eijk*- On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits [p 624]
*L. Ribas-Xirgo and J. Carrabina-Bordoll*

Organizer & Moderator: *Erik Jan Marinissen, Philips Research Labs, The Netherlands co-organized in cooperation with IEEE's Design & Test of Computers*

Speakers: *Karel van Doorselaer, Alcatel Telecom, Belgium Sridhar Narayanan, Sun Microsystems, USA Gert Jan van Rootselaar, Philips Research Labs, The Netherlands *

Moderators: *G. Gielen, Katholieke Universiteit Leuven, Belgium, C. Descleves, Dolphin Integration, France*

- Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
*J. Ecküller, M. Gröpl, and H. Gräb*- EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
*G. Dröge, M. Thole, and E.-H. Horneber*- A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances [p 649]
*L. Hedrich and E. Barke*

Moderators: *A. ten Berg, Philips Research Laboratories, The Netherlands, M. Berkelaar, Eindhoven University of Technology, The Netherlands*

- Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
*D. Ghosh, N. Kapur, J. Harlow III, and F. Brglez*- Technology Mapping for Minimizing Gate and Routing Area [p 664]
*A. Lu, G. Stenz, and F.M. Johannes*- Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
*F. Corno, P. Prinetto, M. Sonza Reorda, and M. Violante*

Moderators: *C. Piguet, CSEM, Switzerland, E. Macii, Politecnico di Torino, Italy*

- Temperature Effect on Delay for Low Voltage Applications [p 680]
*J.M. Daga, E. Ottaviano, and D. Auvergne*- Data Driven Power Optimization of Sequential Circuits [p 686]
*Q. Wang and S.B.K. Vrudhula*- Gated Clock Routing Minimizing the Switched Capacitance [p 692]
*J. Oh and M. Pedram*- Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits [p 698]
*Y.-M. Jiang and K.-T. Cheng*

Co-ordinator: *Ivo Bolsens, IMEC, Belgium*

Moderator: *Ivo Bolsens, IMEC, Belgium*

Speakers: *Norbert Wehn, University of Kaiserslautern, Germany Soren Hein, Siemens, Germany Francky Catthoor, IMEC, Belgium Roelof Salters, Philips Research Labs, The Netherlands *

- Embedded DRAM Architectural Trade-Offs [p 704]
*N. Wehn and S. Hein*- Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology Versus Design Methodology Solutions [p 709]
*F. Catthoor*

Moderators: *J. Franca, IST, Lisbon, Portugal, H. Kerkhoff, University of Twente, The Netherlands*

- Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
*J. Vandenbussche, S. Donnay, F. Leyn, G. Gielen, and W. Sansen*- A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks [p 721]
*R. Rosenberger and S.A. Huss*- Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
*L. Bisdounis, S. Nikolaidis, O. Koufopavlou, and C.E. Goutis*

Moderators: *M. Berkelaar, Eindhoven University of Technology, The Netherlands, L. Stok, IBM T.J. Watson Research Center, USA*

- On Removing Multiple Redundancies in Combinational Circuits [p 738]
*S.-C. Chang, D.I. Cheng, and C.-W. Yeh*- Multi-Output Functional Decomposition with Exploitation of Don't Cares [p 743]
*C. Scholl*- An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
*J.W.J.M. Rutten, M.R.C.M. Berkelaar, C.A.J. van Eijk, and M.A.J. Kolsteren*- Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
*H. Sawada, S. Yamashita, and A. Nagoya*

Moderators: *W. Nebel, University of Oldenburg and OFFIS, Germany, J. Benkoski, Synopsys, France*

- Power Estimation of Behavioral Descriptions [p 762]
*F. Ferrandi, F. Fummi, E. Macii, M. Poncino, and D. Sciuto*- Characterization-Free Behavioral Power Modeling [p 767]
*A. Bogliolo, L. Benini, and G. De Micheli*- Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
*D. Marculescu, R. Marculescu, and M. Pedram*

Moderators: *L. Claesen, IMEC, Belgium, C. Delgado Kloos, ETSI Telecommunicacion, Spain*

- Efficient Verification Using Generalized Partial Order Analysis [p 782]
*S. Vercauteren, D. Verkest, G. de Jong, and B. Lin*- Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
*E. Pastor and J. Cortadella*- Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
*M. Kassab, E. Cerny, S. Aourid, and T. Krodel*- Combinational Verification Based on High-Level Functional Specifications [p 803]
*E.I. Goldberg, Y. Kukimoto, and R.K. Brayton*

Moderators: *A. Richardson, University of Lancaster, UK, M. Sachdev, Philips Research Laboratories, The Netherlands*

- Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
*S. Mir, A. Rueda, D. Vázquez, and J.L. Huertas*- Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]
*M. Renovell, F. Azaïs, and Y. Bertrand*- Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
*W.M. Lindermeir, T.J. Vogels, and H.E. Graeb*

Moderators: *L. Stok, IBM T.J. Watson Research Center, USA A. ten Berg, Philips Research Laboratories, The Netherlands*

- A New Paradigm for Dichotomy-Based Constrained Encoding [p 830]
*O. Coudert*- A Dynamic Model for the State Assignment Problem [p 835]
*M. Martínez, M.J. Avedillo, J.M. Quintana, and J.L. Huertas*- Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
*N. Maheshwari and S.S. Sapatnekar*

Moderators: *M. Pedram, University of Southern California, USA, M. Poncino, Politecnico di Torino, Italy*

- IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
*K.S. Khouri, G. Lakshminarayana, and N.K. Jha*- Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
*H. Tomiyama, T. Ishihara, A. Inoue, and H. Yasuura*- Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
*L. Benini, G. De Micheli, E. Macii, D. Sciuto, and C. Silvano*

Moderators: *M. Kovac, University of Zagreb, Croatia, W. Glauert, University of Erlangen-Nurnberg, Germany*

- A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
*M. Mrva, K. Buchenrieder, and R. Kress*- Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
*V. Salapura and M. Gschwind*- Innovative System-Level Design Environment Based on FORM for Transport Processing System [p 883]
*K. Higuchi and K. Shirakawa*

Moderators: *J.L. Huertas, Centro Nacional de Microelectronica, Spain, J. Pikkarainen, Nokia Mobile Phones, Finland*

- Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
*J.P. Costa, M. Chou, and L.M. Silveira*- Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
*M.W. Tian and C.-J.R. Shi*- An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
*J.A. Prieto, A. Rueda, I. Grout, E. Peralías, J.L. Huertas, and A.M.D. Richardson*

- Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems [p 912]
*R. Niemann and P. Marwedel*- A Knowledge-Based System for Hardware-Software Partitioning [p 914]
*M.L. López, C.A. Iglesias, and J.C. López*- A Formal Description of VHDL-AMS Analogue Systems [p 916]
*T. Kazmierski*- Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
*M.L. Flottes, R. Pires, B. Rouzeyre, and L. Volpe*- Universal Strong Encryption FPGA Core Implementation [p 923]
*D. Runje and M. Kovac*- Data Cache Sizing for Embedded Processor Applications [p 925]
*P.R. Panda, N.D. Dutt, and A. Nicolau*- A Programmable Multi-Language Generator for CoDesign [p 927]
*J.P. Calvez, D. Heller, F. Muller, O. Pasquier*- Register-Constrained Address Computation in DSP Programs [p 929]
*A. Basu, R. Leupers, and P. Marwedel*- Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base [p 931]
*T. Müller-Wipperfürth and R. Hagelauer*- AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]
*G. Economakos, G. Papakonstantinou, and P. Tsanakas*- Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
*S. Olcoz, A. Castellví, M. García, and J.-A. Gómez*- A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor [p 937]
*M.G. Wahl and H. Völkel*- A Comparing Study of Technology Mapping for FPGA [p 939]
*H.-G. Martin and W. Rosenstiel*- Fuzzy-Logic Digital-Analogue Interfaces for Accurate Mixed-Signal Simulation [p 941]
*T.J. Kazmierski*- Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
*W. Sung and S. Ha*- A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
*J.A. Montiel-Nelson, V. de Armas, R. Sarmiento, and A. Núnez*- Architectural Rule Checking for High-Level Synthesis [p 949]
*J. Gong, C.-T. Chen, and K. Kücükcakar*- A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator [p 951]
*H. Kimura and N. Iyenaga*- Core Interconnect Testing Hazards [p 953]
*P. Nordholz, H. Grabinski, D. Treytnar, J. Otterstedt, D. Niggemeyer, U. Arz, and T.W. Williams*- Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
*T. Riesgo, Y. Torroja, E. de la Torre, and J. Uceda*- Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
*C. Bolchini, F. Salice, and D. Sciuto*- IOCIMU -- An Integrated Off-Chip I
_{DDQ}Measurement Unit [p 959] *M. Svajda, B. Straka, and H. Manhaeve*- Automatic Topology Optimization for Analog Module Generators [p 961]
*M. Wolf and U. Kleine*- Asynchronous Scheduling and Allocation [p 963]
*A. Prihozhy*- Path Verification Using Boolean Satisfiability [p 965]
*M. Ringe, T. Lindenkreuz, and E. Barke*- PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
*S. Roy, H. Arts, and P. Banerjee*- Power and Timing Modeling for ASIC Designs [p 969]
*W. Roethig, A.M. Zarkesh, and M. Andrews*- Constraints Space Management for the Layout of Analog IC's [p 971]
*B.G. Arsintescu and R.H.J.M. Otten*- A Synthesis Procedure for Flexible Logic Functions [p 973]
*I. Pomeranz and S.M. Reddy*- Denotational Semantics of a Behavioral Subset of VHDL [p 975]
*F. Nicoli*- Correct High-Level Synthesis: A Formal Perspective [p 977]
*J.M. Mendías, R. Hermida, and M. Fernández*- A Bypass Scheme for Core-Based System Fault Testing [p 979]
*M. Nourani and C. Papachristou*- Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
*C. Metra, M. Favalli, and B. Ricco*- Design-for-Testability for Synchronous Sequential Circuits Using Locally Available Lines [p 983]
*I. Pomeranz and S.M. Reddy*- CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
*S. Pullela, R. Panda, A. Dharchoudhury, G. Vijayan, and D. Blaauw*- Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
*J. Velasco-Medina, T. Calin, and M. Nicolaidis*