DATE 1998 Author Index

[A] [B] [C] [D] [E] [F] [G] [H] [I] [J] [K] [L] [M] [N] [O] [P] [Q] [R] [S] [T] [U] [V] [W] [X] [Y] [Z]

A

Abadir, M.S.: [1] [2] Measuring the Effectiveness of Various Design Validation Approaches for PowerPC^TMMicroprocessor Arrays [p 273]
Adler, T.: [3] [4] An Interactive Router for Analog IC Design [p 414]
Agsteiner, K.: [5] [6] An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Al-Khalili, D.: [7] [8] VHDL Modelling and Analysis of Fault Secure Systems [p 148]
Allara, A.: [9] [10] A Model for System-Level Timed Analysis and Profiling [p 204]
Andrews, M.: [11] [12] Power and Timing Modeling for ASIC Designs [p 969]
Antola, A.: [13] [14] A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
Aourid, S.: [15] [16] Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Arsintescu, B.G.: [17] [18] Constraints Space Management for the Layout of Analog IC's [p 971]
Artigas, J.I.: [19] [20] VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
Arts, H.: [21] [22] PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
Arz, U.: [23] [24] Core Interconnect Testing Hazards [p 953]
Auvergne, D.: [25] [26] Temperature Effect on Delay for Low Voltage Applications [p 680]
Avedillo, M.J.: [27] [28] A Dynamic Model for the State Assignment Problem [p 835]
Ayuda, L.: [29] [30] VHDL Teamwork, Organization Units and Workspace Management [p 297]
Azaïs, F.: [31] [32] Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]

B

Banerjee, P.: [21] [22] PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
Barke, E.: [33] [34] A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances [p 649]; [35] [36] Path Verification Using Boolean Satisfiability [p 965]
Barragán, L.A.: [19] [20] VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
Barriga, A.: [37] [38] XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Basu, A.: [39] [40] Register-Constrained Address Computation in DSP Programs [p 929]
Baur, U.: [41] [42] A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Becker, U.: [43] [44] A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Benini, L.: [45] [46] Characterization-Free Behavioral Power Modeling [p 767]; [47] [48] Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Berkelaar, M.R.C.M.: [49] [50] An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
Bertrand, Y.: [31] [32] Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]
Bisdounis, L.: [51] [52] Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Blaauw, D.: [53] [54] CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Bogliolo, A.: [45] [46] Characterization-Free Behavioral Power Modeling [p 767]
Bogue, T.: [55] [56] Built-In Self-Test with an Alternating Output [p 180]
Bolchini, C.: [57] [58] Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
Böttger, J.: [5] [6] An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Brayton, R.K.: [59] [60] Combinational Verification Based on High-Level Functional Specifications [p 803]
Breuer, M.A.: [61] [62] Scheduling and Module Assignment for Reducing BIST Resources [p 66]
Brglez, F.: [63] [64] Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Bringmann, O.: [65] [66] Cross-Level Hierarchical High-Level Synthesis [p 451]
Buchenrieder, K.: [67] [68] A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]

C

Calin, T.: [69] [70] Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
Calvez, J.P.: [71] [72] A Programmable Multi-Language Generator for CoDesign [p 927]
Carrabina-Bordoll, J.: [73] [74] On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits [p 624]
Castellví, A.: [75] [76] Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Catthoor, F.: [77] [78] Energy-Delay Efficient Data Storage and Transfer Architectures: Circuit Technology Versus Design Methodology Solutions [p 709]
Cerny, E.: [15] [16] Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Chakradhar, S.T.: [79] [80] State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits [p 577]
Chandramouli, V.: [81] [82] AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
Chang, D.: [83] [84] Functional Scan Chain Testing [p 278]
Chang, S.-C.: [85] [86] On Removing Multiple Redundancies in Combinational Circuits [p 738]
Chatzigeorgiou, A.: [87] [88] Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]
Chen, C.-T.: [89] [90] Architectural Rule Checking for High-Level Synthesis [p 949]
Chen, R.M.M.: [91] [92] MCM Interconnect Design Using Two-Pole Approximation [p 544]
Cheng, D.I.: [85] [86] On Removing Multiple Redundancies in Combinational Circuits [p 738]
Cheng, K.-T.: [83] [84] Functional Scan Chain Testing [p 278]; [93] [94] Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits [p 698]
Cheung, H.: [95] [96] Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Choi, H.: [97] [98] Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
Chou, M.: [99] [100] Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
Chu, C.C.N.: [101] [102] A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing [p 479]
Conradi, P.: [103] [104] A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
Coors, M.: [105] [106] FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Coppens, J.: [7] [8] VHDL Modelling and Analysis of Fault Secure Systems [p 148]
Corno, F.: [107] [108] Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]; [109] [110] Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Cortadella, J.: [111] [112] Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
Costa, J.P.: [99] [100] Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
Cota, E.F.: [113] [114] Microsystems Testing: An Approach and Open Problems [p 524]
Coudert, O.: [115] [116] A New Paradigm for Dichotomy-Based Constrained Encoding [p 830]
Courtois, B.: [113] [114] Microsystems Testing: An Approach and Open Problems [p 524]
Crespo, J.: [117] [118] ATM Traffic Shaper: ATS [p 96]
Crossland, W.A.: [95] [96] Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

D

Daga, J.M.: [25] [26] Temperature Effect on Delay for Low Voltage Applications [p 680]
Dave, B.P.: [119] [120] CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]
de Armas, V.: [121] [122] A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
de Jong, G.: [123] [124] Efficient Verification Using Generalized Partial Order Analysis [p 782]
de la Torre, E.: [125] [126] Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
De Loore, B.: [127] [128] IP-Based System-on-a-Chip Design [p 290]
De Micheli, G.: [45] [46] Characterization-Free Behavioral Power Modeling [p 767]; [47] [48] Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Deicke, J.: [129] [130] From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Dharchoudhury, A.: [53] [54] CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Diaz, J.C.: [117] [118] ATM Traffic Shaper: ATS [p 96]
Doboli, A.: [131] [132] Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Donnay, S.: [133] [134] Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Drechsler, R.: [135] [136] Dynamic Minimization of Word-Level Decision Diagrams [p 612]
Dröge, G.: [137] [138] EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
Duarte, R.O.: [139] [140] Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]
Dutt, N.D.: [141] [142] Data Cache Sizing for Embedded Processor Applications [p 925]

E

Ecküller, J.: [143] [144] Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
Economakos, G.: [145] [146] AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]
Eles, P.: [131] [132] Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Ellis, A.: [107] [108] Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Eppler, W.: [147] [148] High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Eshraghian, K.: [95] [96] Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

F

Fassnacht, U.: [149] [150] Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset [p 325]
Favalli, M.: [151] [152] Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
Feldmann, P.: [153] [154] Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Padé Approximation [p 530]
Fernández, M.: [155] [156] Correct High-Level Synthesis: A Formal Perspective [p 977]
Ferrandi, F.: [157] [158] Power Estimation of Behavioral Descriptions [p 762]
Figueras, J.: [159] [160] RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]; [161] [162] Estimation of the Defective I_DDQCaused by Shorts in Deep-Submicron CMOS ICs [p 490]
Fischer, T.: [147] [148] High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Flottes, M.L.: [163] [164] Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Fornaciari, W.: [9] [10] A Model for System-Level Timed Analysis and Profiling [p 204]
Freund, R.W.: [153] [154] Reduced-Order Modeling of Large Linear Passive Multi-Terminal Circuits Using Matrix-Padé Approximation [p 530]
Fummi, F.: [157] [158] Power Estimation of Behavioral Descriptions [p 762]
Furber, S.B.: [165] [166] The Design of an Asynchronous VHDL Synthesizer [p 44]

G

García, J.I.: [19] [20] VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
García, M.: [75] [76] Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Garte, D.: [103] [104] A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
Gasteier, M.: [167] [168] Generation of Interconnect Topologies for Communication Synthesis [p 36]
Gemmeke, H.: [147] [148] High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Gerlach, J.: [169] [170] A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment [p 226]
Ghosh, D.: [63] [64] Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Gielen, G.: [133] [134] Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Glesner, M.: [167] [168] Generation of Interconnect Topologies for Communication Synthesis [p 36]
Goldberg, E.I.: [59] [60] Combinational Verification Based on High-Level Functional Specifications [p 803]
Gómez, J.-A.: [75] [76] Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Gong, J.: [89] [90] Architectural Rule Checking for High-Level Synthesis [p 949]
Gössel, M.: [55] [56] Built-In Self-Test with an Alternating Output [p 180]
Goutis, C.E.: [51] [52] Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Gräb, H.: [143] [144] Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
Grabinski, H.: [23] [24] Core Interconnect Testing Hazards [p 953]
Graeb, H.E.: [171] [172] Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
Grimm, C.: [173] [174] Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
Grode, J.: [175] [176] Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
Gröpl, M.: [143] [144] Hierarchical Characterization of Analog Integrated CMOS Circuits [p 636]
Grötker, T.: [177] [178] A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
Grout, I.: [179] [180] An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Gschwind, M.: [181] [182] Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
Guo, R.: [183] [184] Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]
Gupta, R.K.: [185] [186] An Algorithm to Determine Mutually Exclusive Operations in Behavioral Descriptions [p 457]
Gupta, S.K.: [61] [62] Scheduling and Module Assignment for Reducing BIST Resources [p 66]

H

Ha, S.: [187] [188] Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
Haase, J.: [43] [44] A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Hagelauer, R.: [189] [190] Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base [p 931]
Hamilton, S.N.: [191] [192] Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
Hansen, C.: [193] [194] Verification by Simulation Comparison Using Interface Synthesis [p 436]
Harlow III, J.: [63] [64] Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Hedrich, L.: [33] [34] A Formal Approach to Verification of Linear Analog Circuits with Parameter Tolerances [p 649]
Hein, S.: [195] [196] Embedded DRAM Architectural Trade-Offs [p 704]
Heineken, H.T.: [197] [198] Design-Manufacturing Interface: Part I -- Vision [p 550]; [199] [200] Design-Manufacturing Interface: Part II -- Applications [p 557]; [201] [202] Performance-Manufacturability Tradeoffs in IC Design [p 563]
Hellebrand, S.: [203] [204] Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
Heller, D.: [71] [72] A Programmable Multi-Language Generator for CoDesign [p 927]
Helvig, C.S.: [205] [206] Improved Approximation Bounds for the Group Steiner Problem [p 406]
Hemani, A.: [207] [208] Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
Hermida, R.: [155] [156] Correct High-Level Synthesis: A Formal Perspective [p 977]
Hetzel, A.: [209] [210] A Sequential Detailed Router for Huge Grid Graphs [p 332]
Higuchi, K.: [211] [212] Innovative System-Level Design Environment Based on FORM for Transport Processing System [p 883]
Hollstein, T.: [129] [130] From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Höreth, S.: [135] [136] Dynamic Minimization of Word-Level Decision Diagrams [p 612]
Horneber, E.-H.: [137] [138] EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
Hsiao, M.S.: [79] [80] State Relaxation Based Subsequence Removal for Fast Static Compaction in Sequential Circuits [p 577]
Hsieh, Y.-W.: [213] [214] Model Abstraction for Formal Verification [p 140]
Huertas, J.L.: [215] [216] Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]; [27] [28] A Dynamic Model for the State Assignment Problem [p 835]; [179] [180] An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Huss, S.A.: [217] [218] A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks [p 721]
Hwang, S.H.: [97] [98] Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]

I

Iglesias, C.A.: [219] [220] A Knowledge-Based System for Hardware-Software Partitioning [p 914]
Inoue, A.: [221] [222] Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Ishihara, T.: [221] [222] Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Iyenaga, N.: [223] [224] A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator [p 951]
Izaguirre, I.: [29] [30] VHDL Teamwork, Organization Units and Workspace Management [p 297]

J

Jemai, A.: [225] [226] Architectural Simulation in the Context of Behavioral Synthesis [p 590]
Jerraya, A.A.: [225] [226] Architectural Simulation in the Context of Behavioral Synthesis [p 590]
Jess, J.A.G.: [227] [228] Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]; [229] [230] A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Jha, N.K.: [119] [120] CASPER: Concurrent Hardware-Software Co-Synthesis of Hard Real-Time Aperiodic and Periodic Specifications of Embedded System Architectures [p 118]; [231] [232] IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
Jiang, Y.-M.: [93] [94] Exact and Approximate Estimation for Maximum Instantaneous Current of CMOS Circuits [p 698]
Jiménez, C.J.: [37] [38] XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Jochens, G.: [233] [234] Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Johannes, F.M.: [235] [236] Technology Mapping for Minimizing Gate and Routing Area [p 664]
Jürgensen, H.: [55] [56] Built-In Self-Test with an Alternating Output [p 180]

K

Kahng, A.B.: [237] [238] Interconnect Tuning Strategies for High-Performance ICs [p 471]
Kamon, M.: [239] [240] An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
Kapur, N.: [63] [64] Synthesis of Wiring Signature-Invariant Equivalence Class Circuit Mutants and Applications to Benchmarking [p 656]
Kassab, M.: [15] [16] Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Kaul, M.: [241] [242] Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures [p 389]
Kayss, M.: [129] [130] From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Kazmierski, T.: [243] [244] A Formal Description of VHDL-AMS Analogue Systems [p 916]; [245] [246] Fuzzy-Logic Digital-Analogue Interfaces for Accurate Mixed-Signal Simulation [p 941]
Keding, H.: [105] [106] FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Khare, J.: [197] [198] Design-Manufacturing Interface: Part I -- Vision [p 550]; [199] [200] Design-Manufacturing Interface: Part II -- Applications [p 557]
Khouri, K.S.: [231] [232] IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
Kick, B.: [41] [42] A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Kimura, H.: [223] [224] A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator [p 951]
Kission, P.: [225] [226] Architectural Simulation in the Context of Behavioral Synthesis [p 590]
Kitamura, F.: [247] [248] PASTEL: A Parameterized Memory Characterization System [p 15]
Kleine, U.: [249] [250] Automatic Topology Optimization for Analog Module Generators [p 961]
Knudsen, P.V.: [175] [176] Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
Koegst, M.: [103] [104] A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]
Koehl, J.: [41] [42] A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Kohno, M.: [247] [248] PASTEL: A Parameterized Memory Characterization System [p 15]
Kolsteren, M.A.J.: [49] [50] An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
Koufopavlou, O.: [51] [52] Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Kovac, M.: [251] [252] Universal Strong Encryption FPGA Core Implementation [p 923]
Kress, R.: [67] [68] A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
Krodel, T.: [15] [16] Propagation of Last-Transition-Time Constraints in Gate-Level Timing Analysis [p 796]
Kropf, T.: [253] [254] Formal Specification in VHDL for Hardware Verification [p 257]
Kruse, L.: [233] [234] Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Kuchcinski, K.: [131] [132] Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Kücükcakar, K.: [89] [90] Architectural Rule Checking for High-Level Synthesis [p 949]
Kuh, E.S.: [255] [256] A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction [p 466]
Kukimoto, Y.: [59] [60] Combinational Verification Based on High-Level Functional Specifications [p 803]
Kumar, A.: [207] [208] Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
Kunzmann, A.: [193] [194] Verification by Simulation Comparison Using Interface Synthesis [p 436]
Kurdahi, F.J.: [257] [258] Layout-Driven High Level Synthesis for FPGA Based Architectures [p 446]
Kyung, C.-M.: [97] [98] Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]

L

Lachowicz, S.W.: [95] [96] Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Lago, E.: [37] [38] XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Lakshminarayana, G.: [231] [232] IMPACT: A High-Level Synthesis System for Low Power Control-Flow Intensive Circuits [p 848]
Lee, M.T.-C.: [83] [84] Functional Scan Chain Testing [p 278]
Leijten, J.A.J.: [227] [228] Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]
Leupers, R.: [39] [40] Register-Constrained Address Computation in DSP Programs [p 929]
Levitan, S.P.: [213] [214] Model Abstraction for Formal Verification [p 140]
Leyn, F.: [133] [134] Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Li, J.: [185] [186] An Algorithm to Determine Mutually Exclusive Operations in Behavioral Descriptions [p 457]
Lin, B.: [259] [260] Efficient Compilation of Process-Based Concurrent Programs without Run-Time Scheduling [p 211]; [123] [124] Efficient Verification Using Generalized Partial Order Analysis [p 782]
Lindenkreuz, T.: [35] [36] Path Verification Using Boolean Satisfiability [p 965]
Lindermeir, W.M.: [171] [172] Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
López, D.R.: [37] [38] XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
López, J.C.: [219] [220] A Knowledge-Based System for Hardware-Software Partitioning [p 914]
López, M.L.: [219] [220] A Knowledge-Based System for Hardware-Software Partitioning [p 914]
Lorenz, G.: [43] [44] A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Lu, A.: [235] [236] Technology Mapping for Minimizing Gate and Routing Area [p 664]
Lubaszewski, M.: [113] [114] Microsystems Testing: An Approach and Open Problems [p 524]
Ludwig, T.: [41] [42] A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]

M

Macii, E.: [157] [158] Power Estimation of Behavioral Descriptions [p 762]; [47] [48] Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Madsen, J.: [175] [176] Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System [p 22]
Maestro, J.A.: [261] [262] A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
Maheshwari, N.: [263] [264] Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
Maly, W.: [197] [198] Design-Manufacturing Interface: Part I -- Vision [p 550]; [199] [200] Design-Manufacturing Interface: Part II -- Applications [p 557]; [201] [202] Performance-Manufacturability Tradeoffs in IC Design [p 563]
Manhaeve, H.: [265] [266] A Fully Digital Controlled Off-Chip I_DDQ Measurement Unit [p 495]; [267] [268] IOCIMU -- An Integrated Off-Chip I_DDQMeasurement Unit [p 959]
Marculescu, D.: [269] [270] Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
Marculescu, R.: [269] [270] Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
Marek-Sadowska, M.: [83] [84] Functional Scan Chain Testing [p 278]
Marques, N.: [239] [240] An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
Martin, G.: [271] [272] Design Methodologies for System Level IP [p 286]
Martin, H.-G.: [273] [274] A Comparing Study of Technology Mapping for FPGA [p 939]
Martínez, M.: [27] [28] A Dynamic Model for the State Assignment Problem [p 835]
Marwedel, P.: [275] [276] Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems [p 912]; [39] [40] Register-Constrained Address Computation in DSP Programs [p 929]
Mecha, H.: [261] [262] A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
Menchikov, A.: [147] [148] High Speed Neural Network Chip for Trigger Purposes in High Energy Physics [p 108]
Mendías, J.M.: [155] [156] Correct High-Level Synthesis: A Formal Perspective [p 977]
Mesman, B.: [229] [230] A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Metra, C.: [277] [278] Novel Technique for Testing FPGAs [p 89]; [151] [152] Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
Meyr, H.: [105] [106] FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Mir, S.: [215] [216] Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
Mittwollen, N.: [279] [280] VHDL-AMS: The Missing Link in System Design -- Experiments with Unified Modelling in Automotive Engineering [p 59]
Mojoli, G.: [277] [278] Novel Technique for Testing FPGAs [p 89]
Monjau, D.: [5] [6] An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Montiel-Nelson, J.A.: [121] [122] A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
Moser, E.: [279] [280] VHDL-AMS: The Missing Link in System Design -- Experiments with Unified Modelling in Automotive Engineering [p 59]
Mozos, D.: [261] [262] A Macroscopic Time and Cost Estimation Model Allowing Task Parallelism and Hardware Sharing for the Codesign Partitioning Process [p 218]
Mrva, M.: [281] [282] Enhanced Reuse and Teamwork Capabilities for an Object-Oriented Extension of VHDL [p 250]; [67] [68] A Scalable Architecture for Multi-Threaded JAVA Applications [p 868]
Muddu, S.: [237] [238] Interconnect Tuning Strategies for High-Performance ICs [p 471]
Müller, A.: [177] [178] A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
Muller, F.: [71] [72] A Programmable Multi-Language Generator for CoDesign [p 927]
Müller-Glaser, K.D.: [283] [284] Advanced Optimistic Approaches in Logic Simulation [p 362]
Müller-Wipperfürth, T.: [189] [190] Graphical Entry of FSMDs Revisited: Putting Graphical Models on a Solid Base [p 931]
Münch, M.: [167] [168] Generation of Interconnect Topologies for Communication Synthesis [p 36]
Mutz, M.: [285] [286] Register Transfer Level VHDL Models without Clocks [p 153]

N

Nag, P.K.: [197] [198] Design-Manufacturing Interface: Part I -- Vision [p 550]; [199] [200] Design-Manufacturing Interface: Part II -- Applications [p 557]
Nagoya, A.: [287] [288] Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
Naroska, E.: [289] [290] Parallel VHDL Simulation [p 159]
Navarro, D.: [19] [20] VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]
Nebel, W.: [291] [292] Object-Oriented Modelling of Parallel Hardware Systems [p 234]; [293] [294] A Flexible Message Passing Mechanism for Objective VHDL [p 242]; [233] [234] Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Neul, R.: [43] [44] A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Nicolaidis, M.: [139] [140] Design of Fault-Secure Parity-Prediction Booth Multipliers [p 7]; [69] [70] Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
Nicolau, A.: [141] [142] Data Cache Sizing for Embedded Processor Applications [p 925]
Nicoli, F.: [295] [296] Denotational Semantics of a Behavioral Subset of VHDL [p 975]
Niemann, R.: [275] [276] Synthesis of Communicating Controllers for Concurrent Hardware/Software Systems [p 912]
Niggemeyer, D.: [23] [24] Core Interconnect Testing Hazards [p 953]
Nikolaidis, S.: [87] [88] Collapsing the Transistor Chain to an Effective Single Equivalent Transistor [p 2]; [51] [52] Switching Response Modeling of the CMOS Inverter for Sub-Micron Devices [p 729]
Nordholz, P.: [23] [24] Core Interconnect Testing Hazards [p 953]
Nourani, M.: [297] [298] A Bypass Scheme for Core-Based System Fault Testing [p 979]
Núnez, A.: [121] [122] A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]

O

Öberg, J.: [207] [208] Scheduling of Outputs in Grammar-Based Hardware Synthesis of Data Communication Protocols [p 596]
Ogawa, K.: [247] [248] PASTEL: A Parameterized Memory Characterization System [p 15]
Oh, J.: [299] [300] Gated Clock Routing Minimizing the Switched Capacitance [p 692]
Olcoz, S.: [29] [30] VHDL Teamwork, Organization Units and Workspace Management [p 297]; [75] [76] Static Analysis Tools for Soft-Core Reviews and Audits [p 935]
Orailoglu, A.: [191] [192] Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs [p 604]
Ottaviano, E.: [25] [26] Temperature Effect on Delay for Low Voltage Applications [p 680]
Otten, R.H.J.M.: [17] [18] Constraints Space Management for the Layout of Analog IC's [p 971]
Otterstedt, J.: [23] [24] Core Interconnect Testing Hazards [p 953]
Ouyang, C.: [199] [200] Design-Manufacturing Interface: Part II -- Applications [p 557]
Page, I.: [301] [302] Design of Future Systems [p 343]

P

Panda, P.R.: [141] [142] Data Cache Sizing for Embedded Processor Applications [p 925]
Panda, R.: [53] [54] CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Papachristou, C.: [303] [304] Testing DSP Cores Based on Self-Test Programs [p 166]; [297] [298] A Bypass Scheme for Core-Based System Fault Testing [p 979]
Papakonstantinou, G.: [145] [146] AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]
Park, I.-C.: [97] [98] Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
Parulkar, I.: [61] [62] Scheduling and Module Assignment for Reducing BIST Resources [p 66]
Pasquier, O.: [71] [72] A Programmable Multi-Language Generator for CoDesign [p 927]
Pastor, E.: [111] [112] Efficient Encoding Schemes for Symbolic Analysis of Petri Nets [p 790]
Pastore, S.: [277] [278] Novel Technique for Testing FPGAs [p 89]
Pedram, M.: [299] [300] Gated Clock Routing Minimizing the Switched Capacitance [p 692]; [269] [270] Trace-Driven Steady-State Probability Estimation in FSMs with Application to Power Estimation [p 774]
Penalba, O.: [29] [30] VHDL Teamwork, Organization Units and Workspace Management [p 297]
Peng, Z.: [305] [306] An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis [p 74]; [131] [132] Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Peralías, E.: [179] [180] An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Pflueger, T.: [41] [42] A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset [p 312]
Pires, R.: [163] [164] Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Piuri, V.: [13] [14] A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
Plaza, P.: [117] [118] ATM Traffic Shaper: ATS [p 96]
Pomeranz, I.: [183] [184] Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]; [307] [308] A Synthesis Procedure for Flexible Logic Functions [p 973]; [309] [310] Design-for-Testability for Synchronous Sequential Circuits Using Locally Available Lines [p 983]
Poncino, M.: [157] [158] Power Estimation of Behavioral Descriptions [p 762]
Pop, P.: [131] [132] Scheduling of Conditional Process Graphs for the Synthesis of Embedded Systems [p 132]
Portal, J.M.: [159] [160] RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]
Post, G.: [177] [178] A System-Level Co-Verification Environment for ATM Hardware Design [p 424]
Prieto, J.A.: [179] [180] An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Prihozhy, A.: [311] [312] Asynchronous Scheduling and Allocation [p 963]
Prinetto, P.: [107] [108] Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]; [109] [110] Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Pullela, S.: [53] [54] CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Putzke-Röming, W.: [293] [294] A Flexible Message Passing Mechanism for Objective VHDL [p 242]
Pyttel, A.: [313] [314] PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]

Q

Quintana, J.M.: [27] [28] A Dynamic Model for the State Assignment Problem [p 835]

R

Rabaey, J.: [315] [316] An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
Rabe, D.: [233] [234] Power-Simulation of Cell Based ASICs: Accuracy- and Performance Trade-Offs [p 356]
Radetzki, M.: [293] [294] A Flexible Message Passing Mechanism for Objective VHDL [p 242]
Radhakrishnan, S.: [317] [318] Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
Rassau, A.M.: [95] [96] Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Reddy, S.M.: [183] [184] Procedures for Static Compaction of Test Sequences for Synchronous Sequential Circuits Based on Vector Restoration [p 583]; [307] [308] A Synthesis Procedure for Flexible Logic Functions [p 973]; [309] [310] Design-for-Testability for Synchronous Sequential Circuits Using Locally Available Lines [p 983]
Reetz, R.: [253] [254] Formal Specification in VHDL for Hardware Verification [p 257]
Rencz, M.: [319] [320] Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]
Renovell, M.: [159] [160] RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]; [31] [32] Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits [p 815]
Ribas-Xirgo, L.: [73] [74] On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits [p 624]
Ricco, B.: [151] [152] Highly Testable and Compact 1-out-of-n Code Checker with Single Output [p 981]
Richardson, A.M.D.: [179] [180] An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Riesgo, T.: [125] [126] Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
Ringe, M.: [35] [36] Path Verification Using Boolean Satisfiability [p 965]
Robins, G.: [205] [206] Improved Approximation Bounds for the Group Steiner Problem [p 406]
Rodríguez-Montanés, R.: [161] [162] Estimation of the Defective I_DDQCaused by Shorts in Deep-Submicron CMOS ICs [p 490]
Roethig, W.: [11] [12] Power and Timing Modeling for ASIC Designs [p 969]
Rosenberger, R.: [217] [218] A Systems Theoretic Approach to Behavioural Modeling and Simulation of Analog Functional Blocks [p 721]
Rosenstiel, W.: [169] [170] A Scalable Methodology for Cost Estimation in a Transformational High-Level Design Space Exploration Environment [p 226]; [321] [322] Formal Verification: A New Standard CAD Tool for the Industrial Design Flow [p 422]; [193] [194] Verification by Simulation Comparison Using Interface Synthesis [p 436]; [65] [66] Cross-Level Hierarchical High-Level Synthesis [p 451]; [323] [324] Next Generation System Level Design Tools [p 488]; [273] [274] A Comparing Study of Technology Mapping for FPGA [p 939]
Rouzeyre, B.: [163] [164] Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Roy, S.: [21] [22] PowerShake: A Low Power Driven Clustering and Factoring Methodology for Boolean Expressions [p 967]
Rozon, C.: [7] [8] VHDL Modelling and Analysis of Fault Secure Systems [p 148]
Rudnick, E.M.: [107] [108] Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Rueda, A.: [215] [216] Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]; [179] [180] An Approach to Realistic Fault Prediction and Layout Design for Testability in Analog Circuits [p 905]
Runje, D.: [251] [252] Universal Strong Encryption FPGA Core Implementation [p 923]
Rutten, J.W.J.M.: [49] [50] An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]

S

Sakallah, K.A.: [81] [82] AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
Salapura, V.: [181] [182] Hardware/Software Co-Design of a Fuzzy RISC Processor [p 875]
Salice, F.: [9] [10] A Model for System-Level Timed Analysis and Profiling [p 204]; [57] [58] Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
Salvi, D.: [277] [278] Novel Technique for Testing FPGAs [p 89]
Sami, M.: [13] [14] A Low-Redundancy Approach to Semi-Concurrent Error Detection in Data Paths [p 266]
Sánchez-Solano, S.: [37] [38] XFVHDL: A Tool for the Synthesis of Fuzzy Logic Controllers [p 102]
Sansen, W.: [133] [134] Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Sapatnekar, S.S.: [263] [264] Efficient Minarea Retiming of Large Level-Clocked Circuits [p 840]
Sarmiento, R.: [121] [122] A Cell and Macrocell Compiler for GaAs VLSI Full-Custom Design [p 947]
Sarto, E.: [237] [238] Interconnect Tuning Strategies for High-Performance ICs [p 471]
Sawada, H.: [287] [288] Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
Scheible, J.: [3] [4] An Interactive Router for Analog IC Design [p 414]
Schietke, J.: [149] [150] Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset [p 325]
Schmerler, S.: [283] [284] Advanced Optimistic Approaches in Logic Simulation [p 362]
Schneider, C.: [129] [130] From Algorithms to Hardware Architectures: A Comparison of Regular and Irregular Structured IDCT Algorithms [p 186]
Schneider, K.: [253] [254] Formal Specification in VHDL for Hardware Verification [p 257]
Scholl, C.: [325] [326] Multi-Output Functional Decomposition with Exploitation of Don't Cares [p 743]
Schulze, S.: [5] [6] An Object-Oriented Model for Specification, Prototyping, Implementation and Reuse [p 303]
Schumacher, G.: [291] [292] Object-Oriented Modelling of Parallel Hardware Systems [p 234]
Schwarz, P.: [43] [44] A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]
Sciuto, D.: [9] [10] A Model for System-Level Timed Analysis and Profiling [p 204]; [157] [158] Power Estimation of Behavioral Descriptions [p 762]; [47] [48] Address Bus Encoding Techniques for System-Level Power Optimization [p 861]; [57] [58] Fault Analysis in Networks with Concurrent Error Detection Properties [p 957]
Sechi, G.: [277] [278] Novel Technique for Testing FPGAs [p 89]
Sedlmeier, A.: [313] [314] PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
Shao, J.: [91] [92] MCM Interconnect Design Using Two-Pole Approximation [p 544]
Sharma, R.: [237] [238] Interconnect Tuning Strategies for High-Performance ICs [p 471]
Shen, Z.: [327] [328] An Effective General Connectivity Concept for Clustering [p 398]
Shi, C.-J.R.: [329] [330] Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
Shields Neely, W.: [331] [332] Reconfigurable Logic for Systems on a Chip [p 340]
Shirakawa, K.: [211] [212] Innovative System-Level Design Environment Based on FORM for Transport Processing System [p 883]
Silvano, C.: [47] [48] Address Bus Encoding Techniques for System-Level Power Optimization [p 861]
Silveira, L.M.: [239] [240] An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]; [99] [100] Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC's [p 892]
Simon, P.: [199] [200] Design-Manufacturing Interface: Part II -- Applications [p 557]
Song, J.: [327] [328] An Effective General Connectivity Concept for Clustering [p 398]
Sonza Reorda, M.: [107] [108] Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]; [109] [110] Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Srinivasan, V.: [317] [318] Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]
Stenz, G.: [235] [236] Technology Mapping for Minimizing Gate and Routing Area [p 664]
Straka, B.: [265] [266] A Fully Digital Controlled Off-Chip I_DDQ Measurement Unit [p 495]; [267] [268] IOCIMU -- An Integrated Off-Chip I_DDQMeasurement Unit [p 959]
Strik, M.: [229] [230] A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Sung, W.: [187] [188] Optimized Timed Hardware Software Cosimulation without Roll-Back [p 945]
Svajda, M.: [265] [266] A Fully Digital Controlled Off-Chip I_DDQ Measurement Unit [p 495]; [267] [268] IOCIMU -- An Integrated Off-Chip I_DDQMeasurement Unit [p 959]
Székely, V.: [319] [320] Fast Field Solvers for Thermal and Electrostatic Analysis [p 518]

T

Tan, S.-Y.: [165] [166] The Design of an Asynchronous VHDL Synthesizer [p 44]
Tanurhan, Y.: [283] [284] Advanced Optimistic Approaches in Logic Simulation [p 362]
Thole, M.: [137] [138] EASY -- A System for Computer-Aided Examination of Analog Circuits [p 644]
Tian, M.W.: [329] [330] Efficient DC Fault Simulation of Nonlinear Analog Circuits [p 899]
Timmer, A.H.: [227] [228] Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]; [229] [230] A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Tlili, I.B.S.: [333] [334] March Tests for Word-Oriented Memories [p 501]
Tomiyama, H.: [221] [222] Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Torroja, Y.: [125] [126] Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
Treytnar, D.: [23] [24] Core Interconnect Testing Hazards [p 953]
Tsanakas, P.: [145] [146] AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems [p 933]

U

Uceda, J.: [125] [126] Quality Estimation of Test Vectors and Functional Validation Procedures Based on Fault and Error Models [p 955]
Urriza, I.: [19] [20] VLSI Architecture for Lossless Compression of Medical Images Using the Discrete Wavelet Transform [p 196]

V

van de Goor, A.J.: [333] [334] March Tests for Word-Oriented Memories [p 501]
van Eijk, C.A.J.: [335] [336] Sequential Equivalence Checking without State Space Traversal [p 618]; [49] [50] An Efficient Divide and Conquer Algorithm for Exact Hazard Free Logic Minimization [p 749]
van Meerbergen, J.L.: [227] [228] Stream Communication Between Real-Time Tasks in a High-Performance Multiprocessor [p 125]; [229] [230] A Constraint Driven Approach to Loop Pipelining and Register Binding [p 377]
Vandenbussche, J.: [133] [134] Hierarchical Top-Down Design of Analog Sensor Interfaces: From System-Level Specifications Down to Silicon [p 716]
Vanneuville, J.: [265] [266] A Fully Digital Controlled Off-Chip I_DDQMeasurement Unit [p 495]
Vázquez, D.: [215] [216] Switch-Level Fault Coverage Analysis for Switched-Capacitor Systems [p 810]
Veith, C.: [313] [314] PSCP: A Scalable Parallel ASIP Architecture for Reactive Systems [p 370]
Velasco-Medina, J.: [69] [70] Fault Detection for Linear Analog Circuits Using Current Injection [p 987]
Vemuri, R.: [317] [318] Hardware Software Partitioning with Integrated Hardware Design Space Exploration [p 28]; [241] [242] Optimal Temporal Partitioning and Synthesis for Reconfigurable Architectures [p 389]
Vercauteren, S.: [123] [124] Efficient Verification Using Generalized Partial Order Analysis [p 782]
Verkest, D.: [123] [124] Efficient Verification Using Generalized Partial Order Analysis [p 782]
Vietti, R.: [107] [108] Fast Sequential Circuit Test Generation Using High-Level and Gate-Level Techniques [p 570]
Vijayan, G.: [53] [54] CMOS Combinational Circuit Sizing by Stage-Wise Tapering [p 985]
Violante, M.: [109] [110] Exploiting Symbolic Techniques for Partial Scan Flip Flop Selection [p 670]
Vogels, T.J.: [171] [172] Analog Test Design with IDD Measurements for the Detection of Parametric and Catastrophic Faults [p 822]
Völkel, H.: [337] [338] A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor [p 937]
Volpe, L.: [163] [164] Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique [p 921]
Vrudhula, S.B.K.: [339] [340] Data Driven Power Optimization of Sequential Circuits [p 686]
Vygen, J.: [341] [342] Algorithms for Detailed Placement of Standard Cells [p 321]

W

Wahl, M.: [103] [104] A Systematic Analysis of Reuse Strategies for Design of Electronic Circuits [p 292]; [337] [338] A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor [p 937]
Waldschmidt, K.: [173] [174] Repartitioning and Technology Mapping of Electronic Hybrid Systems [p 52]
Wan, M.: [315] [316] An Energy-Conscious Exploration Methodology for Reconfigurable DSPs [p 341]
Wang, D.: [255] [256] A Performance-Driven MCM Router with Special Consideration of Crosstalk Reduction [p 466]
Wang, L.-C.: [1] [2] Measuring the Effectiveness of Various Design Validation Approaches for PowerPC^TMMicroprocessor Arrays [p 273]
Wang, Q.: [339] [340] Data Driven Power Optimization of Sequential Circuits [p 686]
Wehn, N.: [195] [196] Embedded DRAM Architectural Trade-Offs [p 704]
White, J.: [239] [240] An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models [p 538]
Whittemore, J.P.: [81] [82] AFTA: A Formal Delay Model for Functional Timing Analysis [p 350]
Wilkinson, T.D.: [95] [96] Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]
Willems, M.: [105] [106] FRIDGE: A Fixed-Point Design and Simulation Environment [p 429]
Williams, T.W.: [23] [24] Core Interconnect Testing Hazards [p 953]
Wolf, M.: [249] [250] Automatic Topology Optimization for Analog Module Generators [p 961]
Wong, D.F.: [101] [102] A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing [p 479]
Wunderlich, H.-J.: [203] [204] Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
Wünsche, S.: [43] [44] A Modeling Approach to Include Mechanical Microsystem Components into the System Simulation [p 510]

X

Xu, M.: [257] [258] Layout-Driven High Level Synthesis for FPGA Based Architectures [p 446]

Y

Yamashita, S.: [287] [288] Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions [p 755]
Yang, T.: [305] [306] An Efficient Algorithm to Integrate Scheduling and Allocation in High-Level Test Synthesis [p 74]
Yarmolik, V.N.: [203] [204] Self-Adjusting Output Data Compression: An Efficient BIST Technique for RAMs [p 173]
Yasuura, H.: [221] [222] Instruction Scheduling for Power Reduction in Processor-Based System Design [p 855]
Yeh, C.-W.: [85] [86] On Removing Multiple Redundancies in Combinational Circuits [p 738]
Yen, W.-F.: [165] [166] The Design of an Asynchronous VHDL Synthesizer [p 44]
Yi, J.-H.: [97] [98] Multiple Behavior Module Synthesis Based on Selective Groupings [p 384]
Yu, T.C.B.: [95] [96] Smart Pixel Implementation of a 2-D Parallel Nucleic Wavelet Transform for Mobile Multimedia Communications [p 191]

Z

Zarkesh, A.M.: [11] [12] Power and Timing Modeling for ASIC Designs [p 969]
Zelikovsky, A.: [205] [206] Improved Approximation Bounds for the Group Steiner Problem [p 406]
Zeng, J.: [1] [2] Measuring the Effectiveness of Various Design Validation Approaches for PowerPC^TMMicroprocessor Arrays [p 273]
Zhao, W.: [303] [304] Testing DSP Cores Based on Self-Test Programs [p 166]
Zhuang, W.: [327] [328] An Effective General Connectivity Concept for Clustering [p 398]
Zorian, Y.: [159] [160] RAM-Based FPGA's: A Test Approach for the Configurable Logic [p 82]; [55] [56] Built-In Self-Test with an Alternating Output [p 180]