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Palazzo dei Congressi | 1.1 Opening Session: Plenary, Awards Ceremony & Keynote Addresses | | | | | | | | | |
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Room 1 | | | 2.1 Executive Session 1: Panel "Life After CMOS" | | | 3.1 Executive Session 2: Panel "Semiconductor IP, Surfing the Next Big Wave" | | | | 4.1 Executive Session 3: The Future of Test |
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Exhibition Area | | CB1 Coffee Break | | | | | | CB2 Coffee Break | | |
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Lunch Area | | | | LB1 Lunch Break | | | | | | |
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Poster Area | | | | | | | IP1 Interactive Presentations | | | |
Track 2
Room 2 | | | 2.2 Physical Attacks | | | 3.2 Special Session: Smart Resource Management and Design Space Exploration for Heterogenous Processors | | | | 4.2 Reconfigurable Architecture and Tools |
Track 3
Room 3 | | | 2.3 Special Session: Circuit design and design automation for flexible electronics | | | 3.3 Methods and Characterisation techniques for Reliability | | | | 4.3 Improving test generation and coverage |
Track 4
Room 4 | | | 2.4 Temperature and Variability Driven Modeling and Runtime Management | | | 3.4 Physical Design, Extraction and Timing Analysis | | | | 4.4 Digital processing with emerging memory technologies |
Track 5
Room 5 | | | 2.5 Solutions for reliability and security of mixed-signal circuits | | | 3.5 Hardware authentication and attack prevention | | | | 4.5 Hardware Trojans and Split Manufacturing |
Track 6
Room 6 | | | 2.6 Computational and resource-efficiency in quantum and approximate computing | | | 3.6 Software Solutions for Reliable Memories | | | | 4.6 Smart Communication Solutions for Automotive Systems |
Track 7
Room 7 | | | 2.7 Analysis and optimization techniques for neural networks | | | 3.7 Design Automation of Cyber-Physical Systems | | | | 4.7 Energy and power efficiency in GPU-based systems |
Track 8
Exhibition Theatre | | | 2.8 How Electronic Systems can benefit from Machine Learning and from ESD Alliance | | | 3.8 DFG Collaborative Funding Instruments | | | 3ps.8 Publisher´s Session: How to Publish Your Research Work | |
Track 8
Exh. Theatre | | | | | | | | | | 4.8 Embedded Tutorial: Paving the Way for Very Large Scale Integration of Superconductive Electronics |
Track 0
Room 1 | | | | | 3.0 LUNCH TIME KEYNOTE SESSION | | | | | |
