Track
| X X | | | | | | | | | |
Track
Poster Area | | | IP4 Interactive Presentations | | | | | | IP5 Interactive Presentations | |
Track
Exhibition Area | | | | CB5 Coffee Break | | | | | CB6 Coffee Break | |
Track
Lunch Area | | | | | | LB3 Lunch Break | | | | |
Track 1
Room 1 | | 9.1 Special Day on "Model-Based Design of Intelligent Systems" Session: Experiences from the trenches, model-based design at work | | | 10.1 Special Day on "Model-Based Design of Intelligent Systems" Session: Hot topic: Model-Based Machine Learning | | | 11.1 Special Day on "Model-Based Design of Intelligent Systems" Session: MBD of Cyber-Physical Systems | | 12.1 Special Day on "Model-Based Design of Intelligent Systems" Session: MBD of Safe and Secure Systems |
Track 2
Room 2 | | 9.2 High-Level Synthesis | | | 10.2 Special Session: Enabling Graph Analytics at Extreme Scales: Design Challenges, Advances, and Opportunities | | | 11.2 Novel techniques in optimization and high-level modeling of mixed-signal circuits | | 12.2 The Art of Synthesizing Logic |
Track 3
Room 3 | | 9.3 Special Session: RISC-V or RISK-V? Towards Secure Open Hardware | | | 10.3 System-level Dependability for Multicore and Real-time Systems | | | 11.3 Special Session: Rebooting our Computing Models | | 12.3 Aging, calibration circuits and yield |
Track 4
Room 4 | | 9.4 Where do NoC and Machine Learning meet? | | | 10.4 Disruptive Technologies Ain't Fake News! | | | 11.4 Learning Gets Smarter | | 12.4 Design and Optimization for Low-Power Applications |
Track 5
Room 5 | | 9.5 Attacking Memory and I/O Bottlenecks | | | 10.5 SSD and data placement | | | 11.5 Vitello e Mozzarella alla Fiorentina: Virtualization, Multicore, and Fault-Tolerance | | 12.5 System Modelling for Analysis and Simulation |
Track 6
Room 6 | | 9.6 Reliability of highly-parallel architectures: an industrial perspective | | | 10.6 Self-adaptive resource management | | | 11.6 Design Automation Solutions for Microfluidic Platforms and Tasks | | 12.6 Trojans and public key implementation challenges |
Track 7
Room 7 | | 9.7 Runtime Predictability | | | 10.7 Architectures for emerging machine learning techniques | | | 11.7 Extending Scheduling Schemes | | 12.7 Emerging Strategies for Deep Neural Network Hardware |
Track 8
Exh. Theatre | | 9.8 Special Session: IBM's Qiskit Tool Chain: Developing for and Working with Real Quantum Computers | | | | | | | | |
Track 8
Exhibition Theatre | | | | | 10.8 Europe digitization: Smart Anything Everywhere Initiative & FED4SAE, open calls and success stories | | | 11.8 An Industry Approach to FPGA/ARM System Development and Verification (part 1) | | 12.8 An Industry Approach to FPGA/ARM System Development and Verification (part 2) |
Track 0
Room 1 | | | | | | | 11.0 LUNCH TIME KEYNOTE SESSION | | | |
