Date: Tuesday 26 March 2019
Time: 11:30 - 13:00
Location / Room: Room 1

Organisers:
Marco Casale-Rossi, Synopsys, IT
Jamil Kawa, Synopsys, US

Moderator:
G. Dan Hutcheson, VLSI Research, US

Sixty years ago, Robert Noyce filed U.S. Patent 2,981,877, which marked the birth of the monolithic integrated circuit. Roughly thirty years later, the IC broke the 1-micron barrier — a 100X improvement over Noyce's IC. Today, 7-nanometer is in early manufacturing, and 5-nanometer is under development, marking another 100X improvement. This cannot continue forever: the silicon atom diameter is 2.92 Ångstroms, approximately 0.3 nanometers. Even if we envision the use of atomic layer epitaxy — where we take the cross section of a FET to be that of a single silicon atom source/drain separated by a channel of a single silicon atom vacancy resulting in a handful total available carriers — will it be possible to design and manufacture an IC made of trillions of those transistors in volume? And even if the progress in Moore's law continues relentlessly by going vertical — we have already infringed the second clause of Moore's law: "at the same cost." Yet, the computing and memory requirements of artificial intelligence (AI), biochemistry, medicine, pharmacology, and physics applications greatly exceed the capabilities of current electronics and are unlikely to be met by evolutionary improvements in devices, channel and interconnect materials, or integrated circuit architectures alone. Meeting them means thinking outside the CMOS box. Many are already doing so with circuits based on super-conducting electronics (SCE) and architectures based on quantum computing (QC), where researchers have made significant advances in recent years. In the short term, Josephson junction-based SCE promise to reinvigorate HPC by delivering at least an order of magnitude more performance while using 100-1,000X less power. In the long term, today's foundations for new classes of computers based on the laws of quantum physics — or quantum computers (QC) — may dramatically change the landscape of HPC. They already bring the promise of solving today's intractable problems. This panel, moderated by Dan Hutcheson, brings together some of the industry's greatest thinkers to explore these questions, to color an image of our industry's future, and to go beyond the CMOS box.

Panelists:

• Alessandro Curioni, IBM, CH
  
• Antun Domic, Synopsys, Inc., US
  
• Mark Heiligman, IARPA, US
  
• Buvna Ayyagari-Sangamalli, AMAT, US
  

13:00

End of session Lunch Break in Lunch Area Coffee Breaks in the Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch Breaks (Lunch Area) On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area. Tuesday, March 26, 2019 Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30 Keynote Lecture "Leonardo da Vinci, Humanism and Engineering between Florence and Milan" by Claudio Giorgione in room 1 13:50 - 14:20 Coffee Break 16:00 - 17:00 Wednesday, March 27, 2019 Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30 Keynote Lecture "Heterogeneous, High Scale Computing in the Era of Intelligent, Cloud-Connected" by David Pellerin, Amazon, US in room 1 13:50 - 14:20 Coffee Break 16:00 - 17:00 Thursday, March 28, 2019 Coffee Break 10:00 - 11:00 University Booth Best Demo Award Presentation at the University Booth 10:30 Lunch Break 12:30 - 14:00 Keynote Lecture "A Fundamental Look at Models and Intelligence" by Edward A. Lee, University of California, Berkeley, US in room 1 13:20 - 13:50 Coffee Break 15:30 - 16:00