X X

Printer-friendly version PDF version

Date: Thursday 28 March 2019
Time: 21:00 - 21:00
Location / Room:

TimeLabelPresentation Title
Authors
21:00CHALLENGES AND THE STATUS OF SUPERCONDUCTING SINGLE FLUX QUANTUM TECHNOLOGY
Authors:
Naveen Kumar Katam1, Jamil Kawa2 and Massoud Pedram1
1USC, US; 2Synopsys, US
Abstract
Design and demonstration of superconducting elec- tronics have been evolving over the past three decades and there has been a significant progress in various fields related to it. Rapid single flux quantum (RSFQ) logic circuits have become popular among superconducting logic families and its energy-efficient variations ERSFQ and eSFQ circuits are very promising for low-power and high-speed applications. There are many differences between SFQ logic circuits and conventional CMOS circuits. SFQ logic circuits are based on the manipulation of the quantized magnetic flux pulses. Most of the logic gates are sequential in nature requiring the clock to be distributed to every logic gate. RSFQ circuits were demonstrated at 370 GHz with an energy consumption less than an attojoule per gate. However, there are new challenges in realizing large-scale SFQ circuits that are not encountered in CMOS circuits. Those challenges and the differences with CMOS circuits presented here with a brief introduction into SFQ logic circuits. A status on the demonstrated superconducting CPUs is given to explain the challenges in building them.
21:00PARALLEL WORLDS: LESSONS FROM EXTREME SCALE DATACENTERS
Speaker and Author:
Nicole Hemsoth, The Next Platform, US
Abstract
While there might seem to be little connection between the power efficiency, performance, and price worlds of embedded computing and HPC or hyperscale datacenters, there are more parallels than meet the eye. We will look at how some of the largest datacenter operators in supercomputing and hyperscale are designing next-generation systems from an architectural standpoint and examine the pressures that are driving these choices. In the coming post-Moore's Law era, these forces will drive particular designs to the top—and those could have implications for how computing evolves from the top down.
21:00GRAPH-BASED HARDWARE REPRESENTATION FOR RAPID AND PRECISE PERFORMANCE MODELING
Speaker:
Jan van Lunteren, IBM Research - Zurich, CH
Authors:
Jan van Lunteren, Ronald Luijten, Dionysios Diamantopoulos, Florian Auernhammer, Christoph Hagleitner, Lorenzo Chelini, Stefano Corda and Gagandeep Singh, IBM Research - Zurich, CH
Abstract
The slowdown of Moore's law has caused an escalation in architectural diversity over the last decade, and agile development of domain-specific heterogeneous chips is becoming a high priority. However, this agile development must also consider portable programming environments and other architectural constraints in the system design. More importantly, understanding the role of each component in an end-to-end system design is important to both architects and application developers and must include metrics like power, performance, space, cost, and reliability. Being able to quickly and precisely characterize the needs of an application in the early stages of hardware design is an essential step toward converging on the primary components of these increasingly heterogeneous platforms. In this paper, we introduce FLAME, a graph-based machine representation to flexibly model a given hardware design at any desired resolution while providing the ability to refine specific components along the hierarchy. FLAME allows each processing unit in the system to declare its specific capabilities and enables higher level elements to reuse and leverage these declarations to form more complex system topologies. Applications are characterized with the Aspen application model; each component has the ability to report its characteristic behavior for a given application model against a supported metric. We demonstrate the feasibility of FLAME for several workloads via multi-core machine representations on different levels abstraction.
21:00GRAPH-BASED HARDWARE REPRESENTATION FOR RAPID AND PRECISE PERFORMANCE MODELING
Speaker:
Jeffrey S Vetter, Oak Ridge National Laboratory, US
Authors:
Mehmet E Belviranli and Jeffrey S Vetter, Oak Ridge National Laboratory, US
Abstract
The slowdown of Moore's law has caused an escalation in architectural diversity over the last decade and agile development of domain-specific heterogeneous chips is becoming a high priority. However, this agile development must also consider portable programming environments and other architectural constraints into the system design. More importantly, understanding the role of each component in an end-to-end system design is important to both architects and application developers, and must include metrics like power, performance, space, cost, and reliability. Being able to quickly and precisely characterize the needs of an application in the early stages of hardware design is an essential step towards converging on primary components of these increasingly heterogeneous platforms. In this paper, we introduce FLAME, a graph-based machine representation to flexibly model a given hardware design at any desired resolution while providing the ability to refine specific components along the hierarchy. FLAME allows each processing unit in the system to declare their specific capabilities and enables higher level elements to reuse and leverage these declarations to form more complex system topologies. Applications are characterized with the Aspen application model; each component has the ability to report their characteristic behavior for a given application model against a supported metric. We demonstrate the feasibility of FLAME for several workloads via multi-core machine representations on different levels abstraction.
21:00PANELIST
Author:
Michaela Blott, Xilinx Research, IE
Abstract
tbd
21:00PANELIST
Author:
Ken O'Brien, Xilinx Research, IE
Abstract
tbd
21:00PANELIST
Author:
David Pellerin, Amazon, US
Abstract
tbd
21:00REBOOTING OUR COMPUTING MODELS
Speaker:
Pierre-Emmanuel Gaillardon, University of Utah, US
Authors:
Patsy Cadareanu1, Nagadastagiri Reddy C2, Carmen G. Almudever3, Abhishek Khanna4, Arijit Raychowdhury5, Suman Datta4, koen bertels3, Vijaykrishnan Narayanan2, Massimiliano Di Ventra6 and Pierre-Emmanuel Gaillardon1
1University of Utah, US; 2Penn State, US; 3TU Delft, NL; 4University of Notre Dame, US; 5Georgia Institute of Technology, US; 6University of California, US
Abstract
Innovative and new computing paradigms must be considered as we reach the limits of von Neumann computing caused by the growth in necessary data processing. This paper provides an introduction to three emerging computing models that have established themselves as likely post-CMOS and post-von Neumann solutions. The first of these ideas is quantum computing, for which we discuss the challenges and potential of quantum computer architectures. Next, a computational system using intrinsic oscillators is introduced and an example is provided which shows its superiority in comparison to a typical von Neumann computational system. Finally, digital memcomputing using self-organizing logic gates is explained and then discussed as a method for optimization problems and machine learning.
21:00IBM'S QISKIT TOOL CHAIN: WORKING WITH AND DEVELOPING FOR REAL QUANTUM COMPUTERS
Speaker:
Robert Wille, Johannes Kepler University Linz, AT
Authors:
Robert Wille1, Rod Van Meter2 and Yehuda Naveh3
1Johannes Kepler University Linz, AT; 2Keio University, JP; 3IBM Research, US
Abstract
Quantum computers promise substantial speedups over conventional machines for many practical applications. While considered "dreams of the future" for a long time, first quantum computers are available now which can be utilized by anyone. A leading force within this development is IBM Research which launched the IBM Q Experience - the first industrial initiative to build universal quantum computers and make them accessible to a broad audience through cloud access. Along this initiative, the tool Qiskit has been launched which enables researchers, teachers, developers, and general enthusiasts to write corresponding code and to run experiments on those machines. At the same time, this provides an ideal playground for the design automation community which - through Qiskit - can deploy improved solutions e.g. on designing and realizing quantum applications. This special session summary aims to provide an introduction into Qiskit and is showcasing selected success stories on how to work with and develop for it. In addition to that, it provides corresponding references to further readings in terms of tutorials and scientific papers as well as links to publicly available implementations for Qiskit extensions.
21:00PANELIST
Author:
Jean René Lèquepeys, CEA-Leti, FR
21:00PANELIST
Author:
Alessandro Cremonesi, STMicroelectronics, IT
21:00MODERATOR
Author:
G. Dan Hutcheson, VLSI Research, US
21:00MODERATOR
Author:
Raul Camposano, Sage Design Automation, US
21:00MODERATOR
Author:
Subhasish Mitra, Stanford University, US
21:00End of session
07:30Speakers' breakfast (restricted to the speakers, chairs and co-chairs of the day) in Lunch Area

For speakers and session chairs and co-chairs on the day of their presentation.

An important opportunity to meet other members of your session and receive AV instructions.