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11.2 Novel techniques in optimization and high-level modeling of mixed-signal circuits

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Date: Thursday 28 March 2019
Time: 14:00 - 15:30
Location / Room: Room 2

Chair:
Francisco V. Fernandez, IMSE, ES

Co-Chair:
Mark Po-Hung Lin, National Chung Cheng University, TW

New techniques are presented for the automated behavioral model generation and efficient numerical-symbolic simulation of analog/mixed-signal circuits. Also a Bayesian optimization approach for efficient analog circuit synthesis is presented.

TimeLabelPresentation Title
Authors
14:0011.2.1BEHAVIORAL MODELING OF TRANSISTOR-LEVEL CIRCUITS USING AUTOMATIC ABSTRACTION TO HYBRID AUTOMATA
Speaker:
Ahmad Tarraf, Goethe University Frankfurt, DE
Authors:
Ahmad Tarraf and Lars Hedrich, Goethe University Frankfurt, DE
Abstract
Abstract—Accurate abstracted behavioral modeling of analog circuits is still an open problem, especially when the abstrac- tion process is automated. In this paper we present an auto- mated abstraction technique of transistor level circuits with full SPICE accuracy alongside a significant simulation speed-up. The methodology computes a hybrid automaton which is transformed into a behavioral model in Verilog-A. The resulting hybrid automaton exhibits linear behavior as well as the technology dependent nonlinear e.g. limiting behavior. The accuracy and speed-up of the methodology is evaluated on several transistor level circuits ranging from simple operational amplifiers up to a complex industrial OTA-based Gm/C filter. Finally, we formally verify the equivalence between the generated model and the original circuit. Index Terms—abstraction, verification, hybrid automaton, Verilog-A, behavioral modeling
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14:3011.2.2NUBOLIC SIMULATION OF AMS SYSTEMS WITH DATA FLOW AND DISCRETE EVENT MODELS
Speaker:
Carna Zivkovic, University of Kaiserslautern, DE
Authors:
Carna Zivkovic and Christoph Grimm, TU Kaiserslautern, DE
Abstract
This paper deals with the performance verification of analog/mixed-signal (AMS) systems by symbolic simulation. The approach is to piggyback the symbolic simulation via code-instrumentation on the existing, numeric SystemC AMS simulator. This permits the combination of symbolic and numeric simulation (``nubolic simulation''). The particular focus in the paper is the handling of the symbolic discrete-event process activations. This permits the symbolic simulation of digital parts of AMS systems modeled by discrete event processes. The approach is demonstrated by the symbolic simulation of a dual-charge-pump PLL of an IEEE 802.15.4 RF transceiver that includes an asynchronous digital counter as a frequency divider.
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15:0011.2.3BAYESIAN OPTIMIZATION APPROACH FOR ANALOG CIRCUIT SYNTHESIS USING NEURAL NETWORK
Speaker:
Shuhan Zhang, Fudan University, CN
Authors:
Shuhan Zhang, Wenlong Lv, Fan Yang, Changhao Yan, Dian Zhou and Xuan Zeng, Fudan University, CN
Abstract
Bayesian optimization with Gaussian process as surrogate model has been successfully applied to analog circuit synthesis. In the traditional Gaussian process regression model, the kernel functions are defined explicitly. The computational complexity of training is O(N^3), and the computation complexity of prediction is O(N^2), where N is the number of training data. Gaussian process model can also be derived from a weight space view, where the original data are mapped to feature space, and the kernel function is defined as the inner product of nonlinear features. In this paper, we propose a Bayesian optimization approach for analog circuit synthesis using neural network. We use deep neural network to extract good feature representations, and then define Gaussian process using the extracted features. Model averaging method is applied to improve the quality of uncertainty prediction. Compared to Gaussian process model with explicitly defined kernel functions, the neural-network-based Gaussian process model can automatically learn a kernel function from data, which makes it possible to provide more accurate predictions and thus accelerate the follow-up optimization procedure. Also, the neural-network-based model has O(N) training time and constant prediction time. The efficiency of the proposed method has been verified by two real-world analog circuits.
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15:30IP5-11, 959FINDING ALL DC OPERATING POINTS USING INTERVAL-ARITHMETIC BASED VERIFICATION ALGORITHMS
Speaker:
Itrat A. Akhter, University of British Columbia, CA
Authors:
Itrat Akhter, Justin Reiher and Mark Greenstreet, University of British Columbia, CA
Abstract
This paper applies interval-arithmetic based verification algorithms to circuit verification problems. In particular, we use Krawczyk's operator to find all DC operating points of CMOS circuits. We present what we believe to be the first, completely automatic verification of the Rambus ring-oscillator start-up problem. Comparisons with the dReal and Z3 SMT shows large performance and scalability advantages to the interval verification approach. We provide an open-source implementation that supports state-of-the-art short-channel device models.
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15:30End of session
Coffee Break in Exhibition Area



Coffee Breaks in the Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Lunch Breaks (Lunch Area)

On all conference days (Tuesday to Thursday), a seated lunch (lunch buffet) will be offered in the Lunch Area to fully registered conference delegates only. There will be badge control at the entrance to the lunch break area.

Tuesday, March 26, 2019

Wednesday, March 27, 2019

Thursday, March 28, 2019

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