Date: Wednesday 16 March 2016
Time: 08:30 - 10:00
Location / Room: Konferenz 5

Chair:
Marie-Minerve Louerat, Université Pierre & Marie Curie, (UPMC - Paris 6), FR

Co-Chair:
Christoph Grimm, University of Kaiserslautern, DE

This session presents innovative solutions for test of millimeter-wave circuits, power monitoring, and ADC optimization

Time	Label	Presentation Title Authors
08:30	5.7.1	(Best Paper Award Candidate) BUILT-IN TEST OF MILLIMETER-WAVE CIRCUITS BASED ON NON-INTRUSIVE SENSORS Speaker: Athanasios Dimakos, Université Grenoble Alpes, CNRS, TIMA, FR Authors: Athanasios Dimakos1, Haralampos-G. Stratigopoulos2, Alexandre Siligaris3, Salvador Mir1 and Emeric De Foucauld3 1Université Grenoble Alpes, CNRS, TIMA, FR; 2Sorbonne Universités, UPMC, FR; 3CEA-Leti, FR Abstract This paper addresses the high-volume production test problem for millimeter-wave (mm-Wave) circuits. Bit error rate testing is the only feasible solution nowadays for mm-Wave transceivers, but is extremely costly and challenging to be implemented in high-volume production test floors. The lack of alternative solutions is due to the difficulty in extracting off-chip and processing mm-Wave frequencies. In this paper, we propose a built-in test solution that has two important attributes. First, it is based on non-intrusive sensors that are totally transparent to the mm-Wave circuit. They monitor variations in the performances of the mm-Wave circuit indirectly by virtue of offering an "image" of process variations. Second, the non-intrusive sensors operate at DC or low-frequency, thus dramatically simplifying the test of the mm-Wave circuit. We demonstrate the concept on a 65nm 60GHz mm-Wave low-noise amplifier (LNA). Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	5.7.2	ADAPTIVE DELAY MONITORING FOR WIDE VOLTAGE-RANGE OPERATION Speaker: Jongho Kim, Seoul National University, KR Authors: Jongho Kim1, Gunhee Lee1, Kiyoung Choi1, Yonghwan Kim2, Wook Kim2, Kyungtae Do2 and Jungyun Choi2 1Seoul National University, KR; 2Samsung Electronics, KR Abstract As process technology scales down, circuit delay variations become more and more serious due to manufacturing and environmental variations. The delay variations are hardly predictable and thus require additional design margin and impede the chance to reduce area and power consumption of a chip. One way to alleviate the problem is to measure the circuit delay at run-time and control the supply voltage accordingly through a closed-loop dynamic voltage and frequency scaling (closed-loop DVFS) scheme. The circuit delay is typically measured by a monitoring circuit. However, the key issue of this scheme is the delay mismatch between the monitoring circuit and the target circuit block such as a CPU or a GPU. A large delay mismatch might lose the advantage of closed-loop DVFS. And it becomes worse as the circuit block operates in a wider voltage-range. This paper proposes a novel adaptive delay monitoring scheme for a wide voltage-range operation, which provides a better delay correlation between the monitor and the target compared to conventional monitoring approaches. The proposed approach reduces the average error in the measured delay by up to 45% and the maximum error by up to 68%. The reduction of the error brings the decrease of design margin, resulting in a lower-power and lower-cost design. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	5.7.3	ANALYTICAL DESIGN OPTIMIZATION OF SUB-RANGING ADC BASED ON STOCHASTIC COMPARATOR Speaker: Md. Maruf Hossain, The University of Tokyo, JP Authors: Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura and Kunihiro Asada, The University of Tokyo, JP Abstract An optimal design method for a sub-ranging Analog to Digital Converter (ADC) based on stochastic comparator is demonstrated by performing theoretical analysis of random fluctuations in the comparator offset voltage. The proposed performance model is based on a simple but rigorous Probability Density Function (PDF) for the effective resolution of a stochastic comparator. It is possible to approximately calculate the yield of a stochastic comparator by assuming that the correlations among different analog steps of the output transfer function are negligible. Comparison with Monte Carlo simulation shows that the proposed model precisely estimates the yield of the ADC when it is designed for a reasonable target yield of > 0.8, which is the most practical case while designing a high performance ADC. Application of this model to a stochastic comparator reveals that an additional calibration can significantly enhance the resolution, i.e. it can increase the Number of Bits (NOB) by approximately 2 bits under the same chip yield. Extending the model to a stochastic-comparator-based sub-ranging ADC indicates that the ADC design parameters can be tuned to find the optimal resource distribution between the deterministic coarse stage and the stochastic fine stage. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00	IP2-11, 362	TESTABLE DESIGN OF REPEATERLESS LOW SWING ON-CHIP INTERCONNECT Speaker: Naveen Kadayinti, Indian Institute of Technology Bombay, IN Authors: Naveen Kadayinti and Dinesh Sharma, Indian Institute of Technology Bombay, IN Abstract Repeaterless low swing interconnects use mixed signal circuits to achieve high performance at low power. When these interconnects are used in large scale and high volume digital systems their testability becomes very important. This paper discusses the testability of low swing repeaterless on-chip interconnects with equalization and clock synchronization. A capacitively coupled transmitter with a weak driver is used as the transmitter. The receiver samples the low swing input data at the center of the data eye and converts it to rail to rail levels and also synchronizes the data to the receiver's clock domain. The system is a mixed signal circuit and the digital components are all scan testable. For the analog section, just a DC test has a fault coverage of 50% of the structural faults. Simple techniques allow integration of the analog components into the digital scan chain increasing the coverage to 74%. Finally, a BIST with low overhead enhances the coverage to 95% of the structural faults. The design and simulations have been done in UMC 130 nm CMOS technology. Download Paper (PDF; Only available from the DATE venue WiFi)
10:01	IP2-12, 320	ALL-DIGITAL HYBRID-CONTROL BUCK CONVERTER FOR INTEGRATED VOLTAGE REGULATOR APPLICATIONS Speaker: Visvesh Sathe, University of Washington, US Authors: Ta-tung Yen, Bin Yu and Visvesh Sathe, University of Washington, US Abstract With efficiency and performance gains from subsequent CMOS technology generations continuing to taper-off, power-dissipation remains a roadblock to maintaining growth in computational performance. Power management systems are expected to continue to heavily rely on Dynamic Voltage and Frequency Scaling (DVFS), and Integrated Voltage Regulation (IVR) in particular, to drive improvements in energy-efficiency through finer supply-voltage control. As voltage domains continue to shrink, and multiple IVRs are employed within a System-on-Chip (SoC), all-digital buck converters will become increasingly important from a scalability, portability, and methodology-compatibility perspective. In addition to some of the existing challenges facing Voltage Regulator Modules (VRMs), IVR implementations are faced with additional efficiency and transient response due to the limited available filter capacitance. In this paper, we propose an alldigital hybrid-control buck converter which addresses these key challenges effectively by regulating supply voltage based on slack information from a critical path monitor, a novel and accurate technique for digital derivative measurement for effective PID control, and the use of digital non-linear control for fast transient response. Simulations in an industrial 65nm process technology demonstrate stable, energy-efficient operation with fast load regulation. Operating with a single phase, using package mounted inductor and filter capacitor models, the converter achieves a 25mV droop for a 5A load current ramp at 500mA/ns. With a high-side supply voltage of 2V, the converter achieves a peak efficiency of 86% at 2A. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session Coffee Break in Exhibition Area