9.6 Design, Synthesis and Validation of Analog Circuits
Date: Thursday 12 March 2015
Time: 08:30 - 10:00
Location / Room: Bayard
Chair:
Marie-Minerve Louerat, LIP6/CNRS, FR
Co-Chair:
Georges Gielen, ESAT - KU Leuven, BE
The session presents new synthesis and validation approaches to analog circuit design. Two design papers shade new light on Tunnel FETs and an ADC.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 9.6.1 | KNOWLEDGE-INTENSIVE, CAUSAL REASONING FOR ANALOG CIRCUIT TOPOLOGY SYNTHESIS IN EMERGENT AND INNOVATIVE APPLICATIONS Speakers: Alex Doboli, Fanshu Jiao and Sergio Montano, State University of New York at Stony Brook, US Abstract Analog circuit topology design has been difficult to automate. Topology synthesis involves searching an open-ended, widely extensible, and strongly discontinuous solution space. Existing algorithms cannot generate topologies beyond a constrained set of structures, or experience difficulties in evolving performance-effective yet minimal circuits. This paper proposes a new topology synthesis method that implements a design knowledge-intensive reasoning process to create novel circuit structures with all their features justified by the problem requirements. Two synthesis experiments demonstrate the capability of the method to generate circuits beyond the capabilities of existing topology synthesis algorithms. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 9.6.2 | A CNN-INSPIRED MIXED SIGNAL PROCESSOR BASED ON TUNNEL TRANSISTORS Speakers: Behnam Sedighi, Indranil Palit, Xiaobo Sharon Hu and Michael Niemier, University of Notre Dame, US Abstract Novel devices are under investigation to extend the performance scaling trends that have long been associated with Moore's Law-based device scaling. Among the emerging devices being studied, tunnel FETs (or TFETs) are particularly attractive, especially when targeting low power systems. This paper studies the potential of analog/mixed-signal information processing using TFETs. The design of a highly-parallel processor -- inspired by cellular neural networks -- is presented. Signal processing is performed partially in the time-domain to better leverage the unique properties of TFETs, i.e., (i) steep slopes (high g_m/I_DS) in the subthreshold region, and (ii) high output resistance in the saturation region. Assuming an InAs TFET with feature sizes comparable to the 14 nm technology node, a power efficiency of at least 10,000 GOPS/W is projected. By comparison, state-of-the-art hardware assuming CMOS/FinFET technology promises a power efficiency only close to 1000 GOPS/W. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 9.6.3 | LAYOUT-AWARE SIZING OF ANALOG ICS USING FLOORPLAN & ROUTING ESTIMATES FOR PARASITIC EXTRACTION Speakers: Nuno Lourenco, Ricardo Martins and Nuno Horta, Instituto de Telecomunicações, Instituto Superior Técnico – TU Lisbon, PT Abstract The design of analog integrated circuits (ICs) is characterized by time-consuming and non-systematic iterations between electrical and physical design steps in order to achieve successful post-layout designs. This paper presents an innovative methodology for automatic optimization-based sizing of analog ICs that takes into consideration complete layout-related data for both circuit's geometric requirements, which are obtained from the real-time in-loop floorplan packing, and circuits' electrical performance that is evaluated using circuit simulator and considering accurate layout parasitic estimates. In order to boost the parasitic extraction efficiency, the need for expensive detailed layout generation, as found in previous state-of-the-art layout-aware sizing approaches, is here circumvented. However, the interconnect parasitic capacitances that are major contributors to performance degradation and on-die signal integrity problems, must be accurately accounted for. Therefore, an empirical-based parasitic extraction is performed on an early-stage layout obtained from the floorplan, computing the optimal electromigration-aware wiring topology and shortest rectilinear paths in-loop, without the need for detailed routing. Finally, the methodology is demonstrated for the UMC 130nm design process using well-known analog building blocks proving the generality, accuracy and fast execution of the proposed approach. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:45 | 9.6.4 | INITIAL TRANSIENT RESPONSE OF OSCILLATORS WITH LONG SETTLING TIME Speakers: Hans-Georg Brachtendorf and Bittner Kai, University of Applied Sciences of Upper Austria, AT Abstract The initial transient response of oscillators with high quality factor Q such as quartz crystal oscillators is orders of magnitudes larger than the period of oscillation. Therefore numerical solution by standard techniques of the underlying system of ordinary differential algebraic equations (DAEs) resulting from Kirchhoff's current and voltage laws is run time inefficient. In this paper numerical techniques for the calculation of the initial transient response and steady state solution are investigated. The efficiency results from reformulating the underlying system of ordinary DAEs by a suitable system of partial DAEs, known as multirate PDE, and from suitable finite difference time domain (FDTD) methods with small numerical dissipation of energy. Unlike Harmonic Balance the waveforms are free of spurious oscillations, caused by the non-compactness of the trigonometric polynomials. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP4-14, 191 | AGEING SIMULATION OF ANALOGUE CIRCUITS AND SYSTEMS USING ADAPTIVE TRANSIENT EVALUATION Speakers: Felix Salfelder and Lars Hedrich, Goethe-Universitat Frankfurt a. M., DE Abstract Simulating ageing effects in analogue circuits requires both ageing models and a circuit simulator which is capable of a stress dependent, ageing and recovery aware model evaluation during long term transient simulation. Common approaches on reliability simulation often involve aged models, age precomputation, or lookup tables instead of integrated ageing simulation using memory aware ageing models. Long term transient ageing simulation enhances reliability simulation. This paper presents a framework to model and simulate ageing effects using an adaptive two-times evaluation scheme. This integrates full ageing effect models into behavioural device models. In addition, we introduce semantics for modelling stress levels and ageing parameters in hardware description languages. Our approach is a fully integrated simulation solution, enabling correct and efficient simulation of ageing systems over their lifetimes. We demonstrate how transistor level ageing effects critically affect the operation of a circuit. Our examples incorporate ageing monitors, redundant parts, and self-repair functionality into analogue systems. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:01 | IP4-15, 62 | A TOOL FOR THE ASSISTED DESIGN OF CHARGE REDISTRIBUTION SAR ADCS Speakers: Stefano Brenna1, Andrea Bonetti2, Andrea Bonfanti1 and Andrea L. Lacaita1 1Politecnico di Milano, IT; 2École Polytechnique Fédérale de Lausanne (EPFL), CH Abstract The optimal design of SAR ADCs requires the accurate estimate of nonlinearity and parasitic effects in the feedback charge-redistribution DAC. Since the effects of both mismatch and stray capacitances depend on the specific array topology, complex calculations, custom modeling and heavy simulations in common circuit design environments are often required. This paper presents a MATLAB-based numerical tool to assist the design of the charge redistribution DACs adopted in SAR ADCs. The tool performs both parametric and statistical simulations taking into account capacitive mismatch and parasitic capacitances thus computing both differential and integral nonlinearity (DNL, INL). SNDR and ENoB degradation due to static non-linear effects is also estimated. An excellent agreement is obtained with the results of circuit simulators (e.g. Cadence Spectre) featuring up to 104 shorter simulation time, allowing statistical simulations which would be otherwise impracticable. Measurements on two fabricated SAR ADCs confirm that the proposed tool can be used as avalid instrument to assist the design of a charge redistribution SAR ADC and predict its static and dynamic metrics. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:02 | IP4-16, 140 | DETECTION OF ASYMMETRIC AGING-CRITICAL VOLTAGE CONDITIONS IN ANALOG POWER-DOWN MODE Speakers: Michael Zwerger and Helmut Graeb, Technische Universitaet Muenchen, DE Abstract In this work, a new verification method for the power-down mode of analog circuit blocks is presented. In power-down mode, matched transistors can be stressed with asymmetric voltages. This will cause time-dependent mismatch due to transistor aging. In order to avoid reliability problems, a new method for automatic detection of asymmetric power-down stress conditions is presented. Therefore, power-down voltage-matching rules are formulated. The method combines structural analysis and voltage propagation. Experimental results demonstrate the efficiency and effectiveness of the approach. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:03 | IP4-17, 33 | (Best Paper Award Candidate) HIGH PERFORMANCE SINGLE SUPPLY CMOS INVERTER LEVEL UP SHIFTER FOR MULTI-SUPPLY VOLTAGES DOMAINS Speakers: José-C. García1, Juan A. Montiel-Nelson1, J. Sosa1 and Saeid Nooshabadi2 1Institute for Applied Microelectronics, ES; 2Department of Electrical and Computer Engineering of Michigan Technological University, US Abstract A single supply CMOS inverter level shifter (ssqc-ls) for upconverting signals from 0.4V-1V logic level range up to 1.1V power supply domain is introduced. For guaranteing a low energy consumption, the proposed shifter is based on topological modifications of the structure qc-level shifter reported in [1]. For 0.5V input square wave switching at 500MHz, the inverter level shifter ssqc-ls using 1.2V of power supply achieves a 60% of Figure of Merit improvement in comparison against jy-ls [8] with a dual power supply voltage of 0.6V and 1.2V. Post-layout simulation results shown that ssqc-ls reaches a propagation delay of 0.75ns, an energy consumption of only 2.3pJ, and an energy-delay product of 1.73pJns for a capacitive loading condition of 950fF. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area Coffee Break in Exhibition AreaOn all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch BreakOn Tuesday and Wednesday, lunch boxes will be served in front of the session room Salle Oisans and in the exhibition area for fully registered delegates (a voucher will be given upon registration on-site). On Thursday, lunch will be served in Room Les Ecrins (for fully registered conference delegates only). Tuesday, March 10, 2015Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30; Keynote session from 13:20 - 14:20 (Room Oisans) sponsored by Mentor Graphics Coffee Break 16:00 - 17:00 Wednesday, March 11, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30, Keynote lectures from 12:50 - 14:20 (Room Oisans) Coffee Break 16:00 - 17:00 Thursday, March 12, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00, Keynote lecture from 13:20 - 13:50 Coffee Break 15:30 - 16:00 |
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