Session 1A: Design Optimization of Building Blocks [1]
Session 1B: HW/SW Partitioning and Communication Synthesis [2]
Session 1C: Asynchronous and Hybrid VHDL-Based Design [3]
Session 1D: Data Path and FPGA Testing [4]
Session 2A: Design Methods for High Performance Applications [5]
Session 2B: Scheduling in Embedded Systems [6]
Session 2C: Advanced Techniques for VHDL Design [7]
Session 2D: Novel BIST Approaches [8]
Session 3A: Architectures for Image Processing [9]
Session 3B: Scheduling and Analysis of HW/SW Systems [10]
Session 3C: Extensions to VHDL [11]
Session 3D: Error Detection and Design Validation [12]
Session 3E: Hot Topic: IP Based System-on-a-Chip Design [13]
Session 4A: Design Reuse Methodologies [14]
Session 4B: Flat and Timing-Driven Processor Design [15]
Session 4C: Hot Topic: Reconfigurable Systems [16]
Session 4D: Digital Simulation and Estimation [17]
Session 5A: Synthesis of Reprogrammable and Reconfigurable Architectures [18]
Session 5B: Partitioning and Routing [19]
Session 5C: Panel -- Formal Verification: A New Standard CAD Tool for the Industrial Design Flow [20]
Session 5D: Simulation for High-Level Design [21]
Session 6A: Architectural Synthesis [22]
Session 6B: Timing and Crosstalk in Interconnect [23]
Session 6C: Panel: Next Generation System Design Tools [24]
Session 6D: IDDQ and Memory Testing [25]
Session 7A: Microsystems [26]
Session 7B: Interconnect Modeling [27]
Session 7C: Design for Manufacturability -- Embedded Tutorial [28]
Session 7D: Sequential Circuit Testing [29]
Session 8A: Issues in Behavioral Synthesis [30]
Session 8B: Formal Equivalence Checking Using Decision Diagrams [31]
Session 8C: Hot Topic: Silicon Debug of Systems-on-Chips [32]
Session 8D: Characterization and Verification of Analogue Circuits [33]
Session 9A: Benchmark Circuits, Technology Mapping and Scan Chains [34]
Session 9B: Physical to Gate Level Design for Low-Power [35]
Session 9C: Hot Topic: Embedded Memory and Embedded Logic [36]
Session 9D: Analogue Circuit Modeling and Design Methodology [37]
Session 10A: Combinational Logical Synthesis [38]
Session 10B: High Level Power Estimation [39]
Session 10C: Petri Nets and Dedicated Formalisms [40]
Session 10D: Mixed-Signal Test and DFT [41]
Session 11A: Sequential Logic Synthesis [42]
Session 11B: High-Level Power Optimization [43]
Session 11C: System Architecture Design [44]
Session 11D: Simulation and Test Tools for Analogue Circuits [45]
Poster Session [46]