Date: Thursday 27 March 2014
Time: 10:00 - 12:00
Location / Room: University Booth, Booth 3, Exhibition Area

Label	Presentation Title Authors
UB09.01	SOC VERIFICATION: AUTOMATED FUNCTIONAL VERIFICATION OF SYSTEMS-ON-CHIP Authors: Zdenek Prikryl, Marcela Simkova and Karel Masarik, Faculty of Information Technology, Brno University of Technology, CZ Abstract An increase of the complexity of systems-on-chip (SoC) induces an increase of the complexity of their verification as well. The reason is that we must verify not only the functions of separate logic blocks, but we need to check their interconnections, timing and functional collaboration as well. Therefore, there is still a great demand for verification tools, which are time-effective, fast and as automated as possible. Exactly these issues we target in our solution. You are welcome to see the live demonstration at our booth! More information ...
UB09.02	AN AUTOMATED DESIGN FLOW FOR FAST PROTOTYPING OF SIMULINK MODELS ONTO MPSOC Authors: Francesco Robino and Johnny Öberg, Royal Institute of Technology, SE Abstract Simulink is a modelling environment suitable to model embedded systems at system-level. However there is no standard to rapidly prototype Simulink models onto modern multiprocessor system-on-chip (MPSoC). In this demonstration we show how our NoC System Generator tool can be used as part of an automated platform-based design flow to synthesize a Simulink model to a network-on-chip based MPSoC implementation on FPGA. The performance of the generated prototype scales with the number of processors. More information ...
UB09.03	LARA: THE LARA COMPILER SUITE Authors: Joao Bispo, Pedro Pinto, Ricardo Nobre, Tiago Carvalho and Joao Cardoso, Universidade do Porto, PT Abstract LARA is an aspect-oriented programming (AOP) language which allows the description of sophisticated code instrumentation schemes, advanced mapping strategies including conditional decisions, based on hardware/software resources, and of sophisticated sequences of compiler transformations. Furthermore, LARA provides mechanisms for controlling all elements of a toolchain in a consistent and systematic way, using a unified programming interface. We present three compiler tools developed around the LARA technology, MATISSE, MANET and ReflectC. MATISSE is a compiler which 1) allows analyses and transformations on MATLAB code and 2) generates C code from the MATLAB code. MATISSE can be fully controlled through LARA aspects, which can define the type and shape of MATLAB variables, specify code insertion/removal actions, and define specialization directives and other additional information. MATISSE can output transformed MATLAB code and specialized C code. The knowledge provided by the LARA aspects allows MATISSE to generate C tailored to specific targets (e.g., use statically declared arrays to be compliant with the high-level synthesis tools such as Catapult C). MANET is a source-to-source compiler for ANSI C based on Cetus, and is controlled using LARA aspects. MANET manages to leverage the expressiveness and modularity of LARA to query and manipulate the Cetus AST, providing an easy compilation flow with main goal of code instrumentation and code transformations. LARA aspects allow for a simple selection of program elements in the code which can be analyzed or transformed, by either consulting their attributes or applying actions. Thus, MANET can be used to provide information reports based on compiler analyses, to implement sophisticated code instrumentation strategies, or to perform code optimizations and transformations. ReflectC is a C compiler based on CoSy's compiler framework. CoSy's configurability and retargetability make ReflectC particularly effective for exploration of compiler transformations and optimizations on possible architecture variations, and it is being used for hardware/software co-design and design space exploration (DSE). We will present demos of the tools and the use of LARA aspects and strategies to guide our suite of compilation tools providing: 1) C code generation from MATLAB code, according to information provided by LARA aspects; 2) Instrumentation of C code to be used for collecting specific compile and runtime information (e.g., execution time, range of values for specific variables, custom profiling); 3) User-controlled compiler optimizations targeting several architectures and DSE of sequences of compiler optimizations bearing in mind performance improvements. In addition to presenting examples for each of the tools of the LARA compilation suite, we show an execution of the complete toolchain, controlled by LARA aspects. More information ...
UB09.04	SECURE CLOUD-BASED WORKFLOW-AS-A-SERVICE (WFAAS) ENVIRONMENT WITH ROLE-BASED-ACCESS-CONTROL (RBAC) FOR SOC DESIGN Authors: Sai Manoj P D1, Sai Manoj P. D.1, Hao Yu1 and Joseph Lee2 1Nanyang Technological University, SG; 2Silicon Cloud International, US Abstract The SoC design process requires multiple EDA tools, custom IP's, and technology design kit from multiple providers. The design environment needs to be secure and collaborative. These requirements can be realized by using an integrated cloud based Workflow-as-a-Service (WFaaS) design environment. We demonstrate a cloud-based design environment for a SoC design with multiple CPU cores and analog IO's. This design environment uses an innovative Role-Based-Access-Control user security model where designers interact through a web portal dashboard to perform the design workflows. More information ...
UB09.05	RTL+: DESIGN ENVIRONMENT: WALK BEFORE YOU RUN. Authors: Somayeh Sadeghi-Kohan, Behnaz Pourmohseni, Amir Reza Nekooei, Hanieh Hashemi, Hamed Najafi Haghi and Zainalabedin Navabi, University of Tehran, IR Abstract To enable development of high level designs with hardware correspondence, synthesizability must be satisfied in a top-down manner. Thus in this work, instead of using TLM-2.0 which is not established for synthesis, we will start with a level above RT level, "RTL+". RTL+ is basically using TLM-1.0 channels and includes abstract communications and handshakings that are mainly hidden from the designer. We develop a package of SystemC channels with hardware correspondence (synthesizable HDL) for the communication between various cores (with simple interfaces) and standard buses. More information ...
UB09.06	ENERGY-MODULATED COMPUTING Authors: Maxim Rykunov, Reza Ramezani, Abdullah Baz, Xuefu Zhang, Delong Shang, Andrey Mokhov, Danil Sokolov, Fei Xia and Alex Yakovlev, Newcastle University, GB Abstract This demo will illustrate the principle of energy-modulated computing according to which the flow of energy entering a computing system determines its computational flow. This principle will be fundamental for building future autonomous systems, such as those powered by energy harvesting sources and aimed for survival in power-deficient conditions. The demo includes a set of experimental circuits (with three VLSI chips and PCBs) to work in variable power supply conditions and software tools for digital and analogue co-design (Workcraft, Petrify, MPSAT). More information ...
UB09.07	COMPSOC: VIRTUAL EXECUTION PLATFORMS FOR MIXED TIME-CRITICALITY APPLICATIONS Author: Kees Goossens, TU Eindhoven, NL Abstract System-on-Chip (SOC) design gets increasingly complex, as a growing number of applications are inte- grated in such systems. These applications have mixed time-criticality, i.e., some have firm-, some soft-, and others non-real-time requirements. Executing such a mix of applications on a SOC poses several challenges. First, to reduce cost, platform resources, e.g., processors, interconnect, memories, are shared between applications. However, sharing causes interference between applications, making their behaviors inter- dependent. This results in two problems for SOC design and verification: 1) accurate system-level simulation and several approaches to formal verification are infeasible, because of the explosion in the number of possible combinations of applications, inputs, and resource states and 2) verification becomes a circular process that must be repeated if an application is added, removed, or modified, making integration and verification dominant parts of SOC development, in terms of time and money. The CompSOC platform addresses these problems by executing each application on an independent virtual execution platform (VEP). The VEPs are composable, i.e., cannot affect each other's behaviors. In the temporal domain an applications actual execution never varies by even a single clock cycle. Similarly, the energy and power behaviors of applications are also composable. As a result, applications can be designed, developed, verified, and executed in isolation. The VEPs are also predictable, meaning that all interference is bounded. This makes them virtualized also in terms of performance bounds, which enables firm real-time applications to be verified using formal performance analysis frameworks. The CompSOC platform uses the CoMiK microkernel to implement virtual processors on each processor time through temporal partitioning. Each application can use its own operating system (e.g. Compose, μcOS-III) and model of computation (e.g. CSDF, KPN, TT) in its VEP, to suit its level of time criticality. As more applications are integrated on a single SOC, the need arises for more dynamic behaviour. The system should be able to start, modify and stop applications at run time without affecting running appli- cations. For this purpose the CompSOC platform has been extended with a predictable and composable resource management framework. It manages application bundles that contain 1) an application in the form of executables (ELFs on multiple processors), and also 2) the specifications of the (one or more) particular VEPs that the application executes in, consisting of virtual processors, NOC connections, virtualised mem- ories, etc. At run time, the resource management framework can dynamically load and start application bundles by creating a VEP and then loading, booting, and executing an application within it. VEPs can also be modified, stopped, and deleted at run time. Our University Booth will present virtual-execution-platform and application-bundle concepts using an interactive demonstrator. It will show that the CompSOC has been extended with dynamic functionality, without sacrificing its key strengths: composability and predictability. We will demonstrate this through the use of the resource management framework and application bundles, showing that we can create, modify and delete virtual execution platforms running a mixed time-criticality application dynamically at run-time. More information ...
UB09.09	LEVERAGING DYNAMIC RECONFIGURATION TO INCREASE FAULT-TOLERANCE IN FPGA-BASED SATELLITE SYSTEMS Authors: Sebastian Korf1, Dario Cozzi1, Dirk Jungewelter1, Jens Hagemeyer1, Mario Porrmann1 and Jorgen Ilstad2 1CITEC (Bielefeld University), DE; 2ESTEC (European Space Agency), DE Abstract This demonstrator shows how todays SoCs for satellite payload processing can be extended with high-speed interfaces and computing power utilizing commercial dynamically reconfigurable FPGAs. The use of these FPGAs in space environment will lead to faults due to radiation. Therefore, special methods have been developed to increase the system reliability. We will demonstrate an environment for automatic fault detection and correction in relevant applications like image and video processing. More information ...
UB09.10	UNISON: ASSEMBLY CODE GENERATION USING CONSTRAINT PROGRAMMING Authors: Roberto Castañeda Lozano1, Gabriel Hjort Blindell2, Mats Carlsson1 and Christian Schulte2 1Swedish Institute of Computer Science, SE; 2KTH Royal Institute of Technology, SE Abstract We demonstrate Unison - a simple, flexible and potentially optimal code generator that solves interdependent code generation tasks together using constraint programming as a modern combinatorial optimization method. We show how Unison takes into account the task interdependencies and their combinatorial nature to improve the speed of the code generated by LLVM (a state-of-the-art compiler) for Hexagon (a digital signal processor ubiquitous in modern mobile platforms). More information ...
12:00	End of session
12:30	Lunch Break in Exhibition Area Sandwich lunch