8.3 Test Preparation and Generation

Time	Label	Presentation Title Authors
17:00	8.3.1	ON FUNCTIONAL TEST GENERATION FOR DEEP NEURAL NETWORK IPS Speaker: BO LUO, The Chinese University of Hong Kong, HK Authors: Bo Luo, Yu Li, Lingxiao Wei and Qiang Xu, The Chinese University of Hong Kong, HK Abstract Machine learning systems based on deep neural networks (DNNs) produce state-of-the-art results in many applications. Considering the large amount of training data and know-how required to generate the network, it is more practical to use third-party DNN intellectual property (IP) cores for many designs. No doubt to say, it is essential for DNN IP vendors to provide test cases for functional validation without leaking their parameters. In this paper, we tackle the above problem by judiciously selecting test cases from DNN training samples and applying data augmentation for effective test generation. Experimental results demonstrate the efficacy of our proposed solution. Download Paper (PDF; Only available from the DATE venue WiFi)
17:30	8.3.2	ON SECURE DATA FLOW IN RECONFIGURABLE SCAN NETWORKS Speaker: Pascal Raiola, University of Freiburg, DE Authors: Pascal Raiola¹, Benjamin Thiemann¹, Jan Burchard², Ahmed Atteya³, Natalia Lylina³, Hans-Joachim Wunderlich³, Bernd Becker¹ and Matthias Sauer¹ ¹University of Freiburg, DE; ²Mentor, a Siemens Business, DE; ³University of Stuttgart, DE Abstract Reconfigurable Scan Networks (RSNs) allow flexible access to embedded instruments for post-silicon test, validation and debug or diagnosis. The increased observability and controllability of registers inside the circuit can be exploited by an attacker to leak or corrupt critical information. Precluding such security threats is of high importance but difficult due to complex data flow dependencies inside the reconfigurable scan network as well as across the underlying circuit logic. This work proposes a method that fine-granularly computes dependencies over circuit logic and the RSN. These dependencies are utilized to detect security violations for a given insecure RSN, which is then transformed into a secure RSN. Experimental results demonstrate the applicability of the method to large academical and industrial designs. Additionally, we report on the required effort to mitigate found security violations which also motivates the necessity to consider the circuit logic in addition to pure scan paths. Download Paper (PDF; Only available from the DATE venue WiFi)
18:00	8.3.3	RESYNTHESIS FOR AVOIDING UNDETECTABLE FAULTS BASED ON DESIGN-FOR-MANUFACTURABILITY GUIDELINES Speaker: Naixing Wang, Purdue University, US Authors: Naixing Wang¹, Irith Pomeranz¹, Sudhakar Reddy², Arani Sinha³ and Srikanth Venkataraman³ ¹Purdue University, US; ²University of Iowa, US; ³Intel, US Abstract As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among the faults obtained based on DFM guidelines, there are undetectable faults, and these faults cluster in certain areas of the circuit. Because faults may not perfectly represent potential defect behaviors, defects may be detectable even though the faults that model them are undetectable. Clusters of undetectable faults thus leave areas in the circuit uncovered for potential systematic defects. As the potential defects are systematic, the test escapes can impact the DPPM significantly, and thus lead to circuit malfunction and/or reliability problems after deployment. To address this issue in the context of cell-based design, we propose a logic resynthesis procedure followed by physical design to eliminate large clusters of undetectable faults related to DFM guidelines. The resynthesized circuit maintains design constraints of critical path delay, power consumption and die area. The resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that both the reduction in the numbers of undetectable faults and the reduction in the sizes of undetectable fault clusters are significant. Download Paper (PDF; Only available from the DATE venue WiFi)
18:15	8.3.4	TEST PATTERN GENERATION FOR APPROXIMATE CIRCUITS BASED ON BOOLEAN SATISFIABILITY Speaker: Anteneh Gebregiorgis, Karlsruhe Institute of Technology, DE Authors: Anteneh Gebregiorgis and Mehdi B. Tahoori, Karlsruhe Institute of Technology, DE Abstract Approximate computing has gained growing attention as it provides trade-off between output quality and computation effort for inherent error tolerant applications such as recognition, mining, and media processing applications. As a result, several approximate hardware designs have been proposed in order to harness the benefits of approximate computing. While these circuits are subjected to manufacturing defects and runtime failures, the testing methods should be aware of their approximate nature. In this paper, we propose an automatic test pattern generation methodology for approximate circuit based on boolean satisfiability, which is aware of output quality and approximable vs non-approximable faults. This allows us to significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output quality or test coverage. Experimental results show that, the proposed approach can reduce the fault list by 2.85 on average while maintaining high fault coverage. Download Paper (PDF; Only available from the DATE venue WiFi)
18:30		End of session

Time

Label

Presentation Title
Authors

17:00

8.3.1

ON FUNCTIONAL TEST GENERATION FOR DEEP NEURAL NETWORK IPS
Speaker:
BO LUO, The Chinese University of Hong Kong, HK
Authors:
Bo Luo, Yu Li, Lingxiao Wei and Qiang Xu, The Chinese University of Hong Kong, HK
Abstract
Machine learning systems based on deep neural networks (DNNs) produce state-of-the-art results in many applications. Considering the large amount of training data and know-how required to generate the network, it is more practical to use third-party DNN intellectual property (IP) cores for many designs. No doubt to say, it is essential for DNN IP vendors to provide test cases for functional validation without leaking their parameters. In this paper, we tackle the above problem by judiciously selecting test cases from DNN training samples and applying data augmentation for effective test generation. Experimental results demonstrate the efficacy of our proposed solution.
Download Paper (PDF; Only available from the DATE venue WiFi)

17:30

8.3.2

ON SECURE DATA FLOW IN RECONFIGURABLE SCAN NETWORKS
Speaker:
Pascal Raiola, University of Freiburg, DE
Authors:
Pascal Raiola¹, Benjamin Thiemann¹, Jan Burchard², Ahmed Atteya³, Natalia Lylina³, Hans-Joachim Wunderlich³, Bernd Becker¹ and Matthias Sauer¹
¹University of Freiburg, DE; ²Mentor, a Siemens Business, DE; ³University of Stuttgart, DE
Abstract
Reconfigurable Scan Networks (RSNs) allow flexible access to embedded instruments for post-silicon test, validation and debug or diagnosis. The increased observability and controllability of registers inside the circuit can be exploited by an attacker to leak or corrupt critical information. Precluding such security threats is of high importance but difficult due to complex data flow dependencies inside the reconfigurable scan network as well as across the underlying circuit logic. This work proposes a method that fine-granularly computes dependencies over circuit logic and the RSN. These dependencies are utilized to detect security violations for a given insecure RSN, which is then transformed into a secure RSN. Experimental results demonstrate the applicability of the method to large academical and industrial designs. Additionally, we report on the required effort to mitigate found security violations which also motivates the necessity to consider the circuit logic in addition to pure scan paths.
Download Paper (PDF; Only available from the DATE venue WiFi)

18:00

8.3.3

RESYNTHESIS FOR AVOIDING UNDETECTABLE FAULTS BASED ON DESIGN-FOR-MANUFACTURABILITY GUIDELINES
Speaker:
Naixing Wang, Purdue University, US
Authors:
Naixing Wang¹, Irith Pomeranz¹, Sudhakar Reddy², Arani Sinha³ and Srikanth Venkataraman³
¹Purdue University, US; ²University of Iowa, US; ³Intel, US
Abstract
As integrated circuit manufacturing advances, the occurrence of systematic defects is expected to be prominent. A methodology for predicting potential systematic defects based on design-for-manufacturability (DFM) guidelines was described earlier. In this paper we first report that, among the faults obtained based on DFM guidelines, there are undetectable faults, and these faults cluster in certain areas of the circuit. Because faults may not perfectly represent potential defect behaviors, defects may be detectable even though the faults that model them are undetectable. Clusters of undetectable faults thus leave areas in the circuit uncovered for potential systematic defects. As the potential defects are systematic, the test escapes can impact the DPPM significantly, and thus lead to circuit malfunction and/or reliability problems after deployment. To address this issue in the context of cell-based design, we propose a logic resynthesis procedure followed by physical design to eliminate large clusters of undetectable faults related to DFM guidelines. The resynthesized circuit maintains design constraints of critical path delay, power consumption and die area. The resynthesis procedure is applied to benchmark circuits and logic blocks of the OpenSPARC T1 microprocessor. Experimental results indicate that both the reduction in the numbers of undetectable faults and the reduction in the sizes of undetectable fault clusters are significant.
Download Paper (PDF; Only available from the DATE venue WiFi)

18:15

8.3.4

TEST PATTERN GENERATION FOR APPROXIMATE CIRCUITS BASED ON BOOLEAN SATISFIABILITY
Speaker:
Anteneh Gebregiorgis, Karlsruhe Institute of Technology, DE
Authors:
Anteneh Gebregiorgis and Mehdi B. Tahoori, Karlsruhe Institute of Technology, DE
Abstract
Approximate computing has gained growing attention as it provides trade-off between output quality and computation effort for inherent error tolerant applications such as recognition, mining, and media processing applications. As a result, several approximate hardware designs have been proposed in order to harness the benefits of approximate computing. While these circuits are subjected to manufacturing defects and runtime failures, the testing methods should be aware of their approximate nature. In this paper, we propose an automatic test pattern generation methodology for approximate circuit based on boolean satisfiability, which is aware of output quality and approximable vs non-approximable faults. This allows us to significantly reduce the number of faults to be tested, and test time accordingly, without sacrificing the output quality or test coverage. Experimental results show that, the proposed approach can reduce the fault list by 2.85 on average while maintaining high fault coverage.
Download Paper (PDF; Only available from the DATE venue WiFi)

18:30

End of session