DATE 2021 Best Papers 
| • The DATE 2021 Best Papers | • Best Paper Award Nominations |
DATE Best Paper Awards
Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by the award committee composed of the Track Chairs Ian O'Connor , Theocharis Theocharides, Ilia Polian and Valeria Bertacco and the following members: Lorena Anghel, David Atienza, Koen Bertels, Christos-Savvas Bouganis , Luca Carloni, Stefano Di Carlo, Jose Flich, Pierre-Emmanuel Gaillardon , Tsung-Yi Ho, Artur Jutman, Huichu Liu, Jan Madsen, Maria K. Michael, Francesco Regazzoni, Johanna Sepulveda, Muhammad Shafique, Haralampos Stratigopoulos, Lionel Torres, Jiang Xu, Chengmo Yang.
The DATE 2021 best papers are:
D Track
Leveraging Processor Modeling and Verification for General Hardware Modules
Yue Xing, Huaxi Lu, Aarti Gupta and Sharad Malik
Princeton University
A Track
A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing
Haitao Meng, Chonghao Zho, Jianfeng Gu, Gang Chen
Sun Yat-sen University
T Track
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core
Nils Wistoff1, Moritz Schneider1, Frank Gurkaynak1, Luca Benini2 and Gernot Heiser3
1ETH Zurich, 2Università di Bologna and ETH Zurich, 3UNSW and Data61, CSIRO
E Track
Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns
Paolo Pazzaglia1, Anne Hamann2, Dirk Ziegenbein2 and Martina Maggio3
1Universität des Saarlandes, 2Robert Bosch GmbH, 3Lund University
D Track
Correlated Multi-objective Multi-fidelity Optimization for HLS Directives Design
Qi Sun1, Tinghuan Chen1, Siting Liu1, Jin Miao2, Jianli Chen3, Hao Yu4 and Bei Yu1
1The Chinese University of Hong Kong, 2Cadence Design Systems, 3Fudan University, 4Southern University of Science and Technology
Leveraging Processor Modeling and Verification for General Hardware Modules
Yue Xing, Huaxi Lu, Aarti Gupta and Sharad Malik
Princeton University
3D Heterogeneous ReRAM Architecture for Training Graph Neural Networks
Aqeeb Iqbal Arkal1, Biresh Kumar Joardar1, Jana Doppa1, Partha Pratim Pande1 and Krishnendu Chakrabarty2
1Washington State University, 2Duke University
LSP: Collective Cross-Page Prefetching for NVM
Haiyang Pan, Yuhang Liu, Tianyue Lu and Mingyu Chen
Chinese Academy of Sciences
Efficient Resource Management of Clustered Multi-Processor Systems Through Formal Property Exploration
Ourania Spantidi1, Iraklis Anagnostopoulos1 and Georgios Fainekos2
1Southern Illinois University Carbondale, 2Arizona State University
Margin-Maximization in Binarized Neural Networks for Optimizing Bit Error Tolerance
Sebastian Buschjäger, Jian-Jia Chen, Kuan-Hsun Chen, Mario Günzel, Christian Hakert, Katharina Morik, Rodion Novkin, Lukas Pfahler and Mikail Yayla
Technical University of Dortmund
FPGA Architectures for Approximate Dense SLAM Computing
Maria-Rafaela Gkeka, Alexandros Patras, Christos D. Antonopoulos, Spyros Lalis and Nikolaos Bellas
University of Thessaly
Technology Lookup Table based Default Timing Assertions for Hierarchical Timing Closure
Ravi Ledalla, Chaobo Li, Debjit Sinha, Adil Bhanji, Gregory Schaeffer, Hemlata Gupta and Jennifer Basile
IBM Corporation
COMPACT: Flow-Based Computing on Nanoscale Crossbars with Minimal Semiperimeter
Sven Thijssen1, Sumit Kumar Jha2 and Rickard Ewetz1
1University of Central Florida, 2University of Texas at San Antonio
In-Memory Nearest Neighbor Search with FeFET Multi-Bit Content-Addressable Memories
Arman Kazemi1, Mohammad Mehdi Sharifi1, Ann Franchesca Laguna1, Franz Mueller2, Ramin Rajaei1, Ricardo Olivo2, Thomas Kaempfe2, Michael Niemier1 and X. Sharon Hu1
1University of Notre Dame, 2Fraunhofer IPMS-CNT
A Track
Origin: Enabling On-Device Intelligence for Human Activity Recognition Using Energy Harvesting Wireless Sensor Networks
Cyan Subhra Mishra, John (Jack) Sampson, Mahmut Kandemir and Vijaykrishnan Narayanan
The Pennsylvania State University
A GPU-accelerated Deep Stereo-LiDAR Fusion for Real-time High-precision Dense Depth Sensing
Haitao Meng, Chonghao Zho, Jianfeng Gu and Gang Chen
Sun Yat-sen University
Exploiting Secrets by Leveraging Dynamic Cache Partitioning of Last Level Cache
Anurag Agarwal, Jaspinder Kaur and Shirshendu Das
Indian Institute of Technology Ropar
As Accurate as Needed, as Efficient as Possible: Approximations in DD-based Quantum Circuit Simulation
Stefan Hillmich1, Richard Kueng1, Igor L. Markov2 and Robert Willie1
1Johannes Kepler University Linz, 2University of Michigan
T Track
Characterization and Fault Modeling of Intermediate State Defect in STT-MRAMs
Lizhou Wu1, Siddharth Rao2, Mottaqiallah Taouil1, Erik Jan Marinissen2, Gouri Sankar Kar2 and Said Hamdioui1
1Delft University of Technology, 2IMEC
Device- and Temperature Dependency of Systematic Fault Injection Results in Artix-7 and iCE40 FPGAs
Christian Fibich1, Martin Horauer1 and Roman Obermaisser2
1University of Applied Sciences Technikum Wien, 2University of Siegen
DNN-Life: An Energy-Efficient Aging Mitigation Framework for Improving the Lifetime of On- Chip Weight Memories in Deep Neural Network Hardware Architectures
Muhammad Abdullah Hanif1 and Muhammad Shafique2
1Vienna University of Technology, 2New York University Abu Dhabi
Digital test of ZigBee transmitters: Validation in industrial test environment
Thibault Vayssade1, Florence Azais1, Laurent Latorre1 and François Lefevre2
1Université de Montpellier, 2NXP Semiconductors
Making Obfuscated PUFs Secure Against Power Side-Channel Based Modeling Attacks
Trevor Kroeger1, Wei Cheng2, Sylvain Guilley2, Jean-Luc Danger2 and Naghmeh Karimi1
1University of Maryland, 2Institut Polytechnique de Paris
Microarchitectural Timing Channels and their Prevention on an Open-Source 64-bit RISC-V Core
Nils Wistoff1, Moritz Schneider1, Frank Gurkaynak1, Luca Benini2 and Gernot Heiser3
1ETH Zurich, 2Università di Bologna and ETH Zurich, 3UNSW and Data61, CSIRO
E Track
TinyADC: Peripheral Circuit-aware Weight Pruning Framework for Mixed-signal DNN Accelerators
Geng Yuan1, Payman Benham2, Yuxuan Cai1, Ali Shafiee3, Jingyan Fu4, Zhiheng Liao4, Zhengang Li1, Xiaolong Ma1, Jieren Deng5, Jinhui Wang6, Mahdi Bojnordi2, Yanzhi Wang1 and Caiwen Ding5
1Northeastern University, 2University of Utah, 3Samsung, 4North Dakota State University, 5University of Connecticut, 6University of South Alabama
Adaptive Design of Real-Time Control Systems subject to Sporadic Overruns
Paolo Pazzaglia1, Anne Hamann2, Dirk Ziegenbein2 and Martina Maggio3
1Universität des Saarlandes, 2Robert Bosch GmbH, 3Lund University