Vertical IP Protection of the Next-Generation Devices: Quo Vadis?
Shubham Rai1, Siddharth Garg2, Christian Pilato3, Vladimir Herdt4,5, Elmira Moussavi6, Dominik Sisejkovic6, Ramesh Karri2, Rolf Drechsler4,5, Farhad Merchant6 and Akash Kumar1
1Chair for Processor Design, TU Dresden, Germany
2Center for Cybersecurity, New York University, USA
3Dipartimento di Elettronica, Informazione e Bioingegneria, Politecnico di Milano, Italy
4Institute of Computer Science, Univ. of Bremen, Germany
5Cyber-Physical Systems, DFKI GmbH, Germany
6Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, Germany
ABSTRACT
With the advent of 5G and IoT applications, there is a greater thrust in terms of hardware security due to imminent risks caused by high amount of intercommunication between various subsystems. Security gaps in integrated circuits, thus represent high risks for both—the manufacturers and the users of electronic systems. Particularly in the domain of Intellectual Property (IP) protection, there is an urgent need to devise security measures at all levels of abstraction so that we can be one step ahead of any kind of adversarial attacks. This work presents IP protection measures from multiple perspectives—from systemlevel down to device-level security measures, from discussing various attack methods such as reverse engineering and hardware Trojan insertions to proposing new-age protection measures such as multi-valued logic locking and secure information flow tracking. This special session will give a holistic overview at the current state-of-the-art measures and how well we are prepared for the next generation circuits and systems.
