Memory Hierarchy Calibration Based on Real Hardware In-order Cores for Accurate Simulation
Quentin Huppert1,a, Timon Evenblij2,a Manu Perumkunnil2,b, Francky Catthoor2,c, Lionel Torres1,b and David Novo1,c
1LIRMM, University of Montpellier, CNRS, Montpellier, France
aquentin.huppert@lirmm.fr
blionel.torres@lirmm.frs
cdavid.novo@lirmm.frs
2imec, Leuven, Belgium
atimon.evenblij@imec.be
bmanu.perumkunnil@imec.be
ccatthoor@imec.be
ABSTRACT
Computer system simulators are major tools used by architecture researchers. Two key elements play a role in the credibility of simulator results: (1) the simulator’s accuracy, and (2) the quality of the baseline architecture. Some simulators, such as gem5, already provide highly accurate parameterized models. However, finding the right values for all these parameters to faithfully model a real architecture is still a problem. In this paper, we calibrate the memory hierarchy of an in-order core gem5 simulation to accurately model a real mobile Arm SoC. We execute small programs, which we design to stress specific parts of the memory system, to deduce key parameter values for the model. We compare the execution of SPEC CPU2006 benchmarks on the real hardware with the gem5 simulation. Our results show that our calibration reduces the average and worst-case IPC error by 36% and 50%, respectively, when compared with a gem5 simulation configured with the default parameters.
Keywords: Computer System Simulation, Memory Hierarchy.
