Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP’s T2080 Cache Coherence
Roger Pujol1,2, Hamid Tabani1, Jaume Abella2,3, Mohamed Hassan4 and Francisco J. Cazorla2,3
1Universitat Politecnica de Catalunya, Spain
2Barcelona Supercomputing Center, Spain
3Maspatechnologies S.L., Spain
4McMaster University, Canada
ABSTRACT
The adoption of complex MPSoCs in critical realtime embedded systems mandates a detailed analysis of their architecture to facilitate certification. This analysis is hindered by the lack of a thorough understanding of the MPSoC system due to the unobvious and/or insufficiently documented behavior of some key hardware features. Confidence in those features can only be regained by building specific tests to both, assess whether their behavior matches specifications and unveil their behavior when it is not fully known a priori. In this line, in this work we develop a thorough understanding of the cache coherence protocol in the avionics-relevant NXP T2080 architecture.
