Neuron Fault Tolerance in Spiking Neural Networks
Theofilos Spyrou1, Sarah A. El-Sayed1, Engin Afacan1, Luis A. Camuñas- Mesa2, Bernabé Linares-Barranco2, Haralampos-G. Stratigopoulos1
1Sorbonne Université, CNRS, LIP6, Paris, Francea
2Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC y Universidad de Sevilla, Sevilla, Spain
ABSTRACT
The error-resiliency of Artificial Intelligence (AI) hardware accelerators is a major concern, especially when they are deployed in mission-critical and safety-critical applications. In this paper, we propose a neuron fault tolerance strategy for Spiking Neural Networks (SNNs). It is optimized for low area and power overhead by leveraging observations made from a largescale fault injection experiment that pinpoints the critical fault types and locations. We describe the fault modeling approach, the fault injection framework, the results of the fault injection experiment, the fault-tolerance strategy, and the fault-tolerant SNN architecture. The idea is demonstrated on two SNNs that we designed for two SNN-oriented datasets, namely the N-MNIST and IBM’s DVS128 gesture datasets.
