TRIGON: A Single-phase-clocking Low Power Hardened Flip-Flop with Tolerance to Double-Node-Upset for Harsh Environments Applications
Yan Li1,2,a, Jun Han1,b, Xiaoyang Zeng1,c and Mehdi B. Tahoori2,d
1State Key Laboratory of ASIC & System, School of Microelectronics, Fudan University, Shanghai, China
2Chair of Dependable Nano Computing, Karlsruhe Institute of Technology, Karlsruhe, Germany
aliyan@fudan.edu.cn
bjunhan@fudan.edu.cn
cxyzeng@fudan.edu.cn
dmehdi.tahoori@kit.edu
ABSTRACT
Single Event Upset (SEU) is one of the most susceptible reliability issues for CMOS circuits in a harsh environment, such as space or even a sea-level environment. Especially in the advanced nanoscale node, the phenomenon of Multi-node-upset (MNU) becomes more prominent. Although a lot of work has been proposed to solve this problem, most of them ignored the need for low power consumption. Particularly, most existing solutions are not effective anymore when operating in low supply voltage. Therefore, this paper proposes a novel Flip-Flop called TRIGON based on a single-phaseclocking structure to achieve low power consumption while being able to tolerate Double-node-upset (DNU), even when operating at lower supply voltages. The experimental results show that TRIGON has a significant reduction in the area and Power-delay-area-product (PDAP). Particularly, it achieves about 80% energy saving on average when the input is static compared with the state-of-the-art circuits.
Keywords: Single Event Upset, Low Power, Single-Phaseclocking, Radiation Hardening By Design, Flip-Flop.
