An Efficient Yield Estimation Method for Layouts of High Dimensional and High Sigma SRAM Arrays
Yue Shen1, Changhao Yan1, Sheng-Guo Wang2, Dian Zhou3 and Xuan Zeng1
1State Key Lab of ASIC & System, School of Microelectronics, Fudan University, Shanghai, China
2Dept. of CS, University of North Carolina at Charlotte, Charlotte, USA
3Dept. of EE, University of Texas at Dallas, Dallas, USA
ABSTRACT
This paper firstly focuses on yield estimation problem on post-layout-simulation of high dimensional SRAM arrays. Post-layout-simulation is much more credible than presimulation. However, it introduces strong relationship among SRAM columns. The Multi-Fidelity Gaussian Process model between the small and the large SRAM arrays near Optimal Shift Vector (OSV) is built. An iterative strategy is proposed and Multi-Modal method is applied to obtain more prior knowledge of the small SRAM arrays and further accelerate convergence. Experimental results show that the proposed method can gain 5-7x speedup with less relative errors than the state-of-the-art method for 384D cases.
