Post Silicon Validation of the MMU
Tom Kolan1,a, Hillel Mendelson1,b, Vitali Sokhin1,c, Shai Doron1,d, Hernan Theiler1,e, Shay Aviv1,f, Hagai Hadad1,g, Natalia Freidman1,h, Elena Tsanko2,a, John Ludden2,b, Bryant Cockcroft2,c
1IBM Research
atomk@il.ibm.com
bhillelm@il.ibm.com
cvitali@il.ibm.com
ddshai@il.ibm.com
eHernan.Theiler@il.ibm.com
fShay.Aviv@il.ibm.com
ghagaih@il.ibm.com
hnatalief@il.ibm.com
2IBM Systems & Technology Group
aetsanko@us.ibm.com
bludden@us.ibm.com
ccockcrof@us.ibm.com
ABSTRACT
Post silicon validation is a unique challenge in the design verification process. On one hand, it utilizes real silicon and is therefore able to cover a larger state-space. On the other, it suffers from debugging challenges due to a lack of observability into the design. These challenges dictate distinctive design choices, such as the simplicity of validation tools and a builtfor- debugging software design methodology. The Memory Management Unit (MMU) is central to any design that uses virtual-memory, and creates complex verification challenges, especially in many-core designs.
We propose a novel method for post silicon validation of the MMU that brings together previously undescribed techniques, based on several papers and patents. This method was implemented in Threadmill, a bare metal exerciser and was used in the verification of high-end industry-level POWER and ARM SoCs. It succeeded in increasing RTL coverage, hitting several hidden bugs, and saving hundreds of work-hours in the validation process.
