NBTI Aged Cell Rejuvenation with Back Biasing And Resulting Critical Path Reordering for Digital Circuits in 28nm FDSOI
Ajith Sivadasan1,2,a, Riddhi Jitendrakumar Shah1, Vincent Huard1, Florian Cacho1 and Lorena Anghel2
1STMicroelectronics ‐ 850 rue Jean Monnet, 38926 Crolles, France
aajith.sivadasan@st.com
2TIMA, 46, avenue Félix Viallet, 38031 Grenoble, France
ABSTRACT
Increasing demands from Autonomous Driving and IoT markets are pushing the need for products with advanced CMOS nodes that guarantee a high level of performance and at the same time having to comply with industrial regulatory standards like ISO26262, AEC‐Q100 etc. Implementation of NBTI & DiR Reliability models for 28nm FDSOI, developed in‐house, are fundamental means to evaluate the reliability of digital IPs during the design phase. Process, Temperature, Voltage, Workload based Aging are mission profile parameters traditionally taken into account for design margin evaluations and critical path pruning. A precise critical path selection methodology is highly important considering the In-situ monitor Insertion and Critical Path Replica generation strategies to be applied to Runtime Reliability assessment with the vision to move towards dynamic wear out management solutions. This paper recommends the consideration of the silicon technology feature of back biasing as an important parameter while selecting Critical Paths for circuits fabricated with FDSOI process. Back biasing is an add‐on feature of this technology with ABB (adaptive back biasing) techniques having been used to compensate for PVT variations or aimed at a gain in the overall digital circuit performance. This technique is now being increasingly applied to aging mitigation. The back‐biasing gain for an aged digital IP is quantified while performing design stage Gate Level Analysis yielding interesting insights on its impact on the operational frequency determining critical path rankings.
Keywords: NBTI, Back/Body Biasing, Aging, Critical Path, Reliability.
