Towards Provably‐Secure Performance Locking
Monir Zaman1, Abhrajit Sengupta2, Danqing Liu3, Ozgur Sinanoglu4, Yiorgos Makris1 and Jeyavijayan (JV) Rajendran3
1The University of Texas at Dallas
2New York University
3Texas A&M University
4New York University Abu Dhabi
ABSTRACT
Locking the functionality of an integrated circuit (IC) thwarts attacks such as intellectual property (IP) piracy, hardware Trojans, overbuilding, and counterfeiting. Although functional locking has been extensively investigated, locking the performance of an IC has been little explored. In this paper, we develop provably‐secure performance locking, where only on applying the correct key the IC shows superior performance; for an incorrect key, the performance of the IC degrades significantly. This leads to a new business model, where the companies can design a single IC capable of different performances for different users. We develop mathematical definitions of security and theoretically, and experimentally prove the security against the state‐of‐the‐art‐attacks. We implemented performance locking on a FabScalar microprocessor, achieving a degradation in instructions per clock cycle (IPC) of up to 77% on applying an incorrect key, with an overhead of 0.6%, 0.2%, and 0% for area, power, and delay, respectively.
Keywords: IP piracy, performance locking, Boolean satisfiability (SAT), FabScalar
