ORIENT: Organized Interleaved ECCs for New STT‐MRAM Caches
Zahra Azad 1,a, Hamed Farbeh 2 and Amir Mahdi Hosseini Monazzah 1,b
1Department of Computer Engineering, Sharif University of Technology, Tehran, Iran
azazad@ce.sharif.edu
bahosseini@ce.sharif.edu
2School of Computer Science, Institute for Research in Fundamental Sciences (IPM), Tehran, Iran
farbeh@ipm.ir
ABSTRACT
Spin‐Transfer Torque Magnetic Random Access Memory (STT‐MRAM) is a promising alternative to SRAM in cache memories. However, STT‐MRAMs face with high probability of write errors due to its stochastic switching behavior. To correct the write errors, Error‐Correcting Codes (ECCs) used in SRAM caches are conventionally employed. A cache line consists of several codewords and the data bits are selected in such a way that the maximum correction capability is provided based on the error patterns in SRAMs. However, the different write error patterns in STT‐MRAM caches leads to inefficiency of conventional ECC configurations. In this paper, first we investigate the efficiency of ECC configurations and demonstrate that the vulnerability of codewords in a cache line varies by up to 17x. This variation means that, while some words are overprotected, some others are highly probable to experience uncorrectable errors. Then, we propose an ECC bit selection scheme, so‐called ORIENT, to reduce the vulnerability variation of codewords to 1.4x. The simulation results show that conventional ECC configuration increases the write error rate by up to about 64.4% compared with the optimum ECC bit selection, whereas this value for ORIENT is only 4.5%.
Keywords: STT‐MRAM caches, Error‐correcting codes, Write errors, Interleaving.
