Compact Modeling of Carbon Nanotube Thin Film Transistors for Flexible Circuit Design

Leilai Shao1,4,a, Tsung-Ching Huang4, Ting Lei3, Zhenan Bao3, Raymond Beausoleil4 and Kwang-Ting Cheng 1,2
1University of California, Santa Barbara, CA, USA
2Hong Kong University of Science and Technology, Hong Kong, China
3Stanford University, Stanford, CA, USA
4Hewlett Packard Labs, Palo Alto, CA, USA
alshao@ece.ucsb.edu

ABSTRACT


Carbon nanotube thin film transistor (CNT-TFT) is a promising candidate for flexible electronics, because of its high carrier mobility and great mechanical flexibility. An accurate and trustworthy device model for CNT‐TFTs, however, is still missing. In this paper, we present a SPICE‐compatible compact model for CNT‐TFT circuit simulation and validate the proposed model based on fabricated CNT‐TFTs and Pseudo‐CMOS circuits [1][2]. The proposed CNT‐TFT model enables circuit designers to explore design space by adjusting device parameters, supply voltages and transistor sizes to optimize the noise margin (NM) and power‐delay product (PDP), which are the key merits for larger scale CNT‐TFT circuits. We further propose a design framework to effectively optimize the NM and PDP to facilitate greater automation of flexible circuit design based on CNT‐TFTs.

Keywords: Carbon nanotube, thin‐film transistors, SPICE, Pseudo‐CMOS, robust design, design automation.



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