Design and Integration of Hierarchical‐Placement Multi‐level Caches for Real‐Time Systems
Pedro Benedicte1,2, Carles Hernandez1, Jaume Abella1 and Francisco J. Cazorla1,3
1Barcelona Supercomputing Center
2Universitat Polit ècnica de Catalunya
3IIIA-CSIC
ABSTRACT
Enabling timing analysis in the presence of caches has been pursued by the real‐time embedded systems (RTES) community for years due to cache's huge potential to reduce software's worst‐case execution time (WCET). However, caches heavily complicate timing analysis due to hard‐to‐predict access patterns, with few works dealing with time analyzability of multi‐level cache hierarchies. For measurement‐based timing analysis (MBTA) techniques ‐ widely used in domains such as avionics, automotive, and rail ‐ we propose several cache hierarchies amenable to MBTA. We focus on a probabilistic variant of MBTA (or MBPTA) that requires caches with time‐randomized behavior whose execution time variability can be captured in the measurements taken during system's test runs. For this type of caches, we explore and propose different multi‐level cache setups. From those, we choose a cost‐effective cache hierarchy that we implement and integrate in a 4‐core LEON3 RTL processor model and prototype in a FPGA. Our results show that our proposed setup implemented in RTL results in better (reduced) WCET estimates with similar implementation cost and no impact on average performance w.r.t. other MBPTA‐amenable setups.
