Universal Number Posit Arithmetic Generator on FPGA
Manish Kumar Jaiswala and Hayden K.-H Sob
Dept. of EEE, The University of Hong Kong, Hong Kong
amanishkj@eee.hku.hk
bhso@eee.hku.hk
ABSTRACT
Posit number system format includes a run‐time varying exponent component, defined by a combination of regime‐bit (with run‐time varying length) and exponent‐bit (with size of up to ES bits, the exponent size). This also leads to a run‐time variation in its mantissa field size and position. This run‐time variation in posit format poses a hardware design challenge. Being a recent development, posit lacks for its adequate hardware arithmetic architectures. Thus, this paper is aimed towards the posit arithmetic algorithmic development and their generic hardware generator. It is focused on basic posit arithmetic (floating‐point to posit conversion, posit to floating point conversion, addition/subtraction and multiplication). These are also demonstrated on a FPGA platform. Target is to develop an open source solution for generating basic posit arithmetic architectures with parameterized choices. This contribution would enable further exploration and evaluation of posit system.
Keywords: Unum, Posit, FPGA, Digital Arithmetic, Adder, Subtractor, Multiplier.
