Technical Program

Tuesday, 15 March 2016
1.1	2.1	2.2	2.3	2.4	2.5	2.6	2.7	3.1	3.2	3.3	3.4
3.5	3.6	3.7	IP1	4.1	4.2	4.3	4.4	4.5	4.6	4.7

Wednesday, 16 March 2016
5.1	5.2	5.3	5.4	5.5	5.6	5.7	IP2	6.1	6.2	6.3	6.4
6.5	6.6	6.7	7.0	7.1	7.2	7.3	7.4	7.5	7.6	7.7	IP3
8.1	8.2	8.3	8.4	8.5	8.6	8.7

Thursday, 17 March 2016
9.1	9.2	9.3	9.4	9.5	9.6	9.7	9.8	IP4	10.1	10.2	10.3
10.4	10.5	10.6	10.7	11.0	11.1	11.2	11.3	11.4	11.5	11.6	11.7
IP5	12.1	12.2	12.3	12.4	12.5	12.6	12.7

Session	Opening Session: Plenary, Awards Ceremony & Keynote Addresses
Session Code / Room	1.1 / Großer Saal
Date / Time	Tuesday, 15 March 2016 / 08:30 – 10:30
Chair	Luca Fanucci, University of Pisa, IT
Co-Chair	Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

1.1.1 09:15 – 09:45	[Keynote] From the Happy Few to the Happy Many Towards an Intuitive Internet of Things Luc Van den hove
1.1.2 09:45 – 10:15	[Keynote] Design Will Make Everything Different Antun Domic

Session Title	Executive Track Panel: Enabling a Connected World via Internet of Things
Session Code / Room	2.1 / Saal 2
Date / Time	Tuesday, 15 March 2016 / 11:30 – 13:00
Organiser	Yervant Zorian, Synopsys, US

2.1.1 11:30 – 13:00	Presenter Mohamed Djadoudi
2.1.2 11:30 – 13:00	Presenter Christoph Heer
2.1.3 11:30 – 13:00	Presenter Jamil Kawa
2.1.4 11:30 – 13:00	Presenter Rudy Lauwereins
2.1.5 11:30 – 13:00	Presenter Cheng-Wen Wu

Session Title	Embedded Tutorial: The Dark Silicon Problem: Technology to the Rescue?
Session Code / Room	2. 2 / Konferenz 6
Date / Time	Tuesday, 15 March 2016 / 11:30 – 13:00
Organisers	Siddharth Garg, New York University, US Michael Niemier, University of Notre Dame, South Bend, US
Chair	Muhammad Shafique, Karlsruhe Institute of Technology, DE
Co-Chair	Umit Ogras, Arizona State University, US

2.2.1 11:30 – 12:00	Towards Performance and Reliability-Efficient Computing in the Dark Silicon Era Jörg Henkel, Santiago Pagani, Heba Khdr, Florian Kriebel, Semeen Rehman and Muhammad Shafique
2.2.2 12:00 – 12:30	Towards Near-Threshold Server Processors Ali Pahlevan, Javier Picorel, Arash Pourhabibi Zarandi, Davide Rossi, Marina Zapater, Andrea Bartolini, Pablo G. Del Valle, David Atienza, Luca Benini and Babak Falsafi
2.2.3 12:30 – 13:00	Can Beyond-CMOS Devices Illuminate Dark Silicon? Robert Perricone, X. Sharon Hu, Joseph Nahas and Michael Niemier

Session Title	Automotive Systems and Smart Energy Systems
Session Code / Room	2.3 / Konferenz 1
Date / Time	Tuesday, 15 March 2016 / 11:30 – 13:00
Chair	David Boyle, Imperial College London, GB
Co-Chair	Felix Reimann, Audi Electronics Venture, DE

2.3.1 11:30 – 12:00	OTEM: Optimized Thermal and Energy Management for Hybrid Electrical Energy Storage in Electric Vehicles Korosh Vatanparvar and Mohammad Abdullah Al Faruque
2.3.2 12:00 – 12:30	Supertask: Maximizing Runnable-level Parallelism in AUTOSAR Applications Sebastian Kehr, Miloš Panić, Eduardo Quiñones, Bert Böddeker, Jorge Becerril Sandoval, Jaume Abella, Francisco J. Cazorla and Günter Schäfer
2.3.3 12:30 – 12:45	Formal Analysis Based Evaluation of Software Defined Networking for Time-Sensitive Ethernet Daniel Thiele and Rolf Ernst
2.3.4 12:45 – 13:00	Accelerated Artificial Neural Networks on FPGA for Fault Detection in Automotive Systems Shanker Shreejith, Bezborah Anshuman and Suhaib A. Fahmy

Session Title	Physical Design for Cutting-edge Lithography
Session Code / Room	2.4 / Konferenz 2
Date / Time	Tuesday, 15 March 2016 / 11:30 – 13:00
Chair	Jens Lienig, Technische Universität Dresden, DE
Co-Chair	Patrick Groeneveld, Synopsys Inc., US

2.4.1 11:30 – 12:00	Optimization for Multiple Patterning Lithography with Cutting Process and Beyond Jian Kuang and Evangeline F. Y. Young
2.4.2 12:00 – 12:30	A Fast Manufacturability Aware Optical Proximity Correction (OPC) Algorithm with Adaptive Wafer Image Estimation Ahmed Awad, Atsushi Takahashi and Chikaaki Kodama
2.4.3 12:30 – 12:45	Redundant Via Insertion in Directed Self-Assembly Lithography Woohyun Chung, Seongbo Shim and Youngsoo Shin
2.4.4 12:45 – 13:00	Improved Performance of 3DIC Implementations Through Inherent Awareness of Mix-and-Match Die Stacking Kwangsoo Han, Andrew B. Kahng and Jiajia Li

Session Title	Energy Efficient Systems and Architectures
Session Code / Room	2.5 / Konferenz 3
Date / Time	Tuesday, 15 March 2016 / 11:30 – 13:00
Chair	Mladen Berekovic, TU Braunschweig, DE
Co-Chair	Rolf Ernst, TU Braunschweig, DE

2.5.1 11:30 – 12:00	A Discrete Thermal Controller for Chip-Multiprocessors Yingnan Cui, Wei Zhang and Bingsheng He
2.5.2 12:00 – 12:30	Swallow: Building an Energy-Transparent Many-Core Embedded Real-Time System Simon J. Hollis and Steve Kerrison
2.5.3 12:30 – 12:45	A Novel Cache-Utilization Based Dynamic Voltage Frequency Scaling (DVFS) Mechanism for Reliability Enhancements Yen-Hao Chen, Yi-Lun Tang, Yi-Yu Liu, Allen C.-H. Wu and TingTing Hwang
2.5.4 12:45 – 13:00	Efficient Kernel Management on GPUs Xiuhong Li and Yun Liang

Session Title	Fault-Tolerant Embedded Systems
Session Code / Room	2.6 / Konferenz 4
Date / Time	Tuesday, 15 March 2016 / 11:30 – 13:00
Chair	Lothar Thiele, ETH Zurich, CH
Co-Chair	Jian-Jia Chen, TU Dortmund, DE

2.6.1 11:30 – 12:00	Probabilistic WCET Estimation in Presence of Hardware for Mitigating the Impact of Permanent Faults Damien Hardy, Isabelle Puaut and Yiannakis Sazeides
2.6.2 12:00 – 12:30	A Four-Mode Model for Efficient Fault-Tolerant Mixed-Criticality Systems Zaid Al-bayati, Jonah Caplan, Brett H. Meyer and Haibo Zeng
2.6.3 12:30 – 13:00	Providing Formal Latency Guarantees for ARQ-based Protocols in Networks-on-Chip Eberle A. Rambo, Selma Saidi and Rolf Ernst

Session Title	Variability Challenges in Nanoscale Designs
Session Code / Room	2.7 / Konferenz 5
Date / Time	Tuesday, 15 March 2016 / 11:30 – 13:00
Chair	Vikas Chandra, ARM Research, US
Co-Chair	Said Hamdioui, TU Delft, NL

2.7.1 11:30 – 12:00	Achieving 100% Cell-Aware Coverage by Design Zeye (Dexter) Liu, Ben Niewenhuis, Soumya Mittal and R. D. (Shawn) Blanton
2.7.2 12:00 – 12:30	Modeling Fabrication Non-Uniformity in Chip-Scale Silicon Photonic Interconnects Mahdi Nikdast, Gabriela Nicolescu, Jelena Trajkovic and Odile Liboiron-Ladouceur
2.7.3 12:30 – 13:00	Efficient Spatial Variation Modeling via Robust Dictionary Learning Changhai Liao, Jun Tao, Xuan Zeng, Yangfeng Su, Dian Zhou and Xin Li

Session Title	Executive Track Panel: New Opportunities in Automotive Electronics
Session Code / Room	3.1 / Saal 2
Date / Time	Tuesday, 15 March 2016 / 14:30 – 16:00
Organiser	Yervant Zorian, Synopsys, US

3.1.1 14:30 – 16:00	Presenter Josef Stockinger
3.1.2 14:30 – 16:00	Presenter Rainer Kress
3.1.3 14:30 – 16:00	Presenter Dan Kochpatcharin
3.1.4 14:30 – 16:00	Presenter Frank Schirrmeister

Session Title	Hot Topic: 3D ICs: Leap Forward to 1,000X Performance
Session Code / Room	3.2 / Konferenz 6
Date / Time	Tuesday, 15 March 2016 / 14:30 – 16:00
Organiser	Vikas Chandra, ARM, US
Chair	Vikas Chandra, ARM, US
Co-Chair	Norbert Wehn, University of Kaiserslautern, DE

3.2.1 14:30 – 15:00	The N3XT 1,000X Subhasish Mitra, Stanford University, US
3.2.2 15:00 – 15:30	3D Sequential Integration for Monolithic 3DIC Design Olivier Billoint, CEA-Leti, FR
3.2.3 15:30 – 14:30	3D Technology Driven by 3D Application Requirements: A 3D-Landscape for 3D System Design Dragomir Milojevic, IMEC, BE

Session Title	On-Chip Security Testing
Session Code / Room	3.3 / Konferenz 1
Date / Time	Tuesday, 15 March 2016 / 14:30 – 16:00
Chair	Giorgio Di Natale, LIRMM, FR
Co-Chair	Marc Witteman, Riscure, NL

3.3.1 14:30 – 15:00	TOTAL: TRNG On-the-fly Testing for Attack Detection using Lightweight Hardware Bohan Yang, Vladimir Rožic, Nele Mentens, Wim Dehaene and Ingrid Verbauwhede
3.3.2 15:00 – 15:30	On-chip Fingerprinting of IC Topology for Integrity Verification Maxime Lecomte, Jacques J.A. Fournier and Philippe Maurine
3.3.3 15:30 – 16:00	Activation of Logic Encrypted Chips: Pre-Test or Post-Test? Muhammad Yasin, Samah Mohamed Saeed, Jeyavijayan (JV) Rajendran and Ozgur Sinanoglu

Session Title	Application-specific Low-power Techniques
Session Code / Room	3.4 / Konferenz 2
Date / Time	Tuesday, 15 March 2016 / 14:30 – 16:00
Chair	Sheldon X.-D. Tan, University of California at Riverside, US
Co-Chair	Masaaki Kondo, University of Tokyo, JP

3.4.1 14:30 – 15:00	Multiplier-less Artificial Neurons Exploiting Error Resiliency for Energy-Efficient Neural Computing Syed Shakib Sarwar, Swagath Venkataramani, Anand Raghunathan and Kaushik Roy
3.4.2 15:00 – 15:30	Significance Driven Hybrid 8T-6T SRAM for Energy-Efficient Synaptic Storage in Artificial Neural Networks Gopalakrishnan Srinivasan, Parami Wijesinghe, Syed Shakib Sarwar, Akhilesh Jaiswal and Kaushik Roy
3.4.3 15:30 – 16:00	Network Delay-Aware Energy Management for Mobile Systems Minho Ju, Hyeonggyu Kim and Soontae Kim

Session Title	Emerging Devices and Methodologies for Energy Efficient Systems
Session Code / Room	3.5 / Konferenz 3
Date / Time	Tuesday, 15 March 2016 / 14:30 – 16:00
Chair	Mehdi Tahoori, Karlsruhe Institute of Technology, DE
Co-Chair	Aida Todri-Sanial, LIRMM, FR

3.5.1 14:30 – 15:00	Enabling Simultaneously Bi-Directional TSV Signaling for Energy and Area Efficient 3D-ICs Sunghyun Park, Alice Wang, Uming Ko, Li-Shiuan Peh and Anantha P. Chandrakasan
3.5.2 15:00 – 15:30	Reconfigurable Nanowire Transistors with Multiple Independent Gates for Efficient and Programmable Combinational Circuits Jens Trommer, André Heinzig, Tim Baldauf, Thomas Mikolajick, Walter M. Weber, Michael Raitza and Marcus Völp
3.5.3 15:30 – 16:00	Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking Luca Amarú, Pierre-Emmanuel Gaillardon, Robert Wille and Giovanni De Micheli

Session Title	Timing Analysis and Measurement
Session Code / Room	3.6 / Konferenz 4
Date / Time	Tuesday, 15 March 2016 / 14:30 – 16:00
Chair	Marko Bertogna, Università di Modena e Reggio Emilia, IT
Co-Chair	Damien Hardy, University of Rennes 1/IRISA, FR

3.6.1 14:30 – 15:00	Conservative Modeling of Shared Resource Contention for Dependent Tasks in Partitioned Multi-Core Systems Junchul Choi, Donghyun Kang and Soonhoi Ha
3.6.2 15:00 – 15:30	Formal Worst-Case Timing Analysis of Ethernet TSN’s Burst-Limiting Shaper Daniel Thiele and Rolf Ernst
3.6.3 15:30 – 15:45	Real-Time Analysis of Engine Control Applications with Speed Estimation Alessandro Biondi and Giorgio Buttazzo
3.6.4 15:45 – 16:00	Trace-based Analysis Methodology of Program Flash Contention in Embedded Multicore Systems Lin Li and Albrecht Mayer

Session Title	Dealing with Runtime Failures
Session Code / Room	3.7 / Konferenz 5
Date / Time	Tuesday, 15 March 2016 / 14:30 – 16:00
Chair	Lorena Anghel, TIMA Laboratory, FR
Co-Chair	Michel Renovell, LIRMM, FR

3.7.1 14:30 – 15:00	A Cross-Layer Analysis of Soft Error, Aging and Process Variation in Near Threshold Computing Anteneh Gebregiorgis, Saman Kiamehr, Fabian Oboril, Rajendra Bishnoi and Mehdi B. Tahoori
3.7.2 15:00 – 15:30	Fast-yet-accurate Variation-Aware Current and Voltage Modelling of Radiation-Induced Transient Fault Hsuan-Ming (Ryan) Huang, Yuwen (Dave) Lin and Charles H.-P. Wen
3.7.3 15:30 – 15:45	A Detailed Methodology to Compute Soft Error Rates in Advanced Technologies Marc Riera, Ramon Canal, Jaume Abella and Antonio Gonzalez
3.7.4 15:45 – 16:00	Analysis of NBTI Effects on High Frequency Digital Circuits Ahmet Unutulmaz, Domenik Helms, Reef Eilers, Malte Metzdorf, Ben Kaczer and Wolfgang Nebel

Session Title	Interactive Presentations
Session Code / Room	IP1
Date / Time	Tuesday, 15 March 2016 / 16:00 – 16:30

IP1-1	A Scalable Lane Detection Algorithm on COTSs with OpenCL Kai Huang, Biao Hu, Jan Botsch, Nikhil Madduri and Alois Knoll
IP1-2	Simulation of Falling Rain for Robustness Testing of Video-Based Surround Sensing Systems Dennis Hospach, Stefan Mueller, Wolfgang Rosenstiel and Oliver Bringmann
IP1-3	Proposal for Fast Directional Energy Interchange Used in MCMC-Based Autonomous Decentralized Mechanism toward Resilient Microgrid Yusuke Sakumoto and Ittetsu Taniguchi
IP1-4	Grid-based Self-Aligned Quadruple Patterning Aware Two Dimensional Routing Pattern Takeshi Ihara, Toshiyuki Hongo, Atsushi Takahashi and Chikaaki Kodama
IP1-5	Practical ILP-based Routing of Standard Cells Hsueh-Ju Lu, En-Jang Jang, Ang Lu, Yu Ting Zhang, Yu-He Chang, Chi-Hung Lin and Rung-Bin Lin
IP1-6	A Procedure for Improving the Distribution of Congestion in Global Routing Daohang Shi, Azadeh Davoodi and Jeffrey Linderoth
IP1-7	Machine Learned Machines: Adaptive Co-optimization of Caches, Cores, and On-chip Network Rahul Jain, Preeti Ranjan Panda and Sreenivas Subramoney
IP1-8	Improving Performance by Monitoring While Maintaining Worst-Case Guarantees Syed Md Jakaria Abdullah, Kai Lampka and Wang Yi
IP1-9	Fault Tolerant Non-Volatile Spintronic Flip-Flop Rajendra Bishnoi, Fabian Oboril and Mehdi B. Tahoori
IP1-10	Towards Automatic Diagnosis of Minority Carriers Propagation Problems in HV/HT Automotive Smart Power ICs Yasser Moursy, Hao Zou, Ramy Iskander, Pierre Tisserand, Dieu-My Ton, Giuseppe Pasetti, Ehrenfried Seebacher, Alexander Steinmair, Thomas Gneiting and Heidrun Alius
IP1-12	Towards a Highly Reliable SRAM-based PUFs Elena Ioana Vatajelu, Giorgio Di Natale and Paola Prinetto
IP1-13	Current based PUF Exploiting Random Variations in SRAM Cells Fengchao Zhang, Shuo Yang, Jim Plusquellic and Swarup Bhunia
IP1-14	Behavioral Modeling of Timing Slack Variation in Digital Circuits Due to Power Supply Noise Taesik Na and Saibal Mukhopadhyay
IP1-15	Lossless Compression Algorithm Based on Dictionary Coding for Multiple E-Beam Direct Write System Pei-Chun Lin, Yu-Hsuan Pai, Yu-Hsiang Chiu, Shao-Yuan Fang and Charlie Chung-Ping Chen
IP1-16	PhoNoCMap: an Application Mapping Tool for Photonic Networks-on-Chip Edoardo Fusella and Alessandro Cilardo
IP1-17	Design of an Efficient Ready Queue for Earliest-Deadline-First (EDF) Scheduler Risat Mahmud Pathan
IP1-18	RT Level Timing Modeling for Aging Prediction Nils Koppaetzky, Malte Metzdorf, Reef Eilers, Domenik Helms and Wolfgang Nebel

Session Title	Executive Track Panel: Trends & Challenges to Ensure Security
Session Code / Room	4.1 / Saal 2
Date / Time	Tuesday, 15 March 2016 / 17:00 – 18:30
Organiser	Yervant Zorian, Synopsys, US

4.1.1 17:00 – 18:30	Presenter Mike Borza
4.1.2 17:00 – 18:30	Presenter Rob Aitken
4.1.3 17:00 – 18:30	Presenter Serge Leef

Session Title	Hot Topic: Nanoelectronic Design Tools Addressing Coupled Problems for 3D-IC Integration
Session Code / Room	4.2 / Konferenz 6
Date / Time	Tuesday, 15 March 2016 / 17:00 – 18:30
Organisers	Jan ter Maten, University of Wuppertal, DE Caren Tischendorf, Humboldt University of Berlin, DE
Chair	Wim Schoenmaker, Magwel NV, Leuven, BE
Co-Chair	Caren Tischendorf, Humboldt University of Berlin, DE

4.2.1 17:00 – 17:22	Fast Time-Domain Simulation for Reliable Fault Detection Bratislav Tasić, Jos J. Dohmen, Rick Janssen, E. Jan W. ter Maten, Roland Pulch and Theo G. J. Beelen
4.2.2 17:22 – 17:44	Holistic Coupled Field and Circuit Simulation Wim Schoenmaker, Peter Meuris, Christian Strohm and Caren Tischendorf
4.2.3 17:44 – 18:06	Model Order Reduction for Nanoelectronics Coupled Problems with Many Inputs N. Banagaaya, L. Feng, W. Schoenmaker, P. Meuris, A. Wieers, R. Gillonz and P. Benner
4.2.4 18:06 – 17:00	Shape Optimization of a Power MOS Device Under Uncertainties Piotr Putek, Peter Meuris, Roland Pulch, E. Jan W. ter Maten, Michael Günther, Wim Schoenmaker, Frederik Deleu and Aarnout Wieers

Session Title	Firmware Security
Session Code / Room	4.3 / Konferenz 1
Date / Time	Tuesday, 15 March 2016 / 17:00 – 18:30
Chair	Nele Mentens, Katholieke Universiteit Leuven, BE
Co-Chair	Aurelien Francillon, EURECOM, FR

4.3.1 17:00 – 17:30	Practical Evaluation of Code Injection in Encrypted Firmware Updates Oscar M. Guillen, Dawin Schmidt and Georg Sigl
4.3.2 17:30 – 18:00	Integration of ROP/JOP Monitoring IPs in an ARM-based SoC Yongje Lee, Jinyong Lee, Ingoo Heo, Dongil Hwang and Yunheung Paek
4.3.3 18:00 – 18:30	Verifying Information Flow Properties of Firmware using Symbolic Execution Pramod Subramanyan, Sharad Malik, Hareesh Khattri, Abhranil Maiti and Jason Fung

Session Title	System-level Energy Management
Session Code / Room	4.4 / Konferenz 2
Date / Time	Tuesday, 15 March 2016 / 17:00 – 18:30
Chair	William Fornaciari, Politecnico di Milano – DEIB, IT
Co-Chair	Soontae Kim, KAIST, KR

4.4.1 17:00 – 17:30	Low-Overhead Adaptive Constrast Enhancement and Power Reduction for OLEDs Daniele Jahier Pagliari, Massimo Poncino and Enrico Macii
4.4.2 17:30 – 18:00	Dynamic Energy Burst Scaling for Transiently Powered Systems Andres Gomez, Lukas Sigrist, Michele Magno, Luca Benini and Lothar Thiele
4.4.3 18:00 – 17:00	Low-power Multichannel Spectro-temporal Feature Extraction Circuit for Audio Pattern Wake-up Dinko Oletic, Vedran Bilas, Michele Magno, Norbert Felber and Luca Benini

Session Title	Ultra-low Energy Memory Devices
Session Code / Room	4.5 / Konferenz 3
Date / Time	Tuesday, 15 March 2016 / 17:00 – 18:30
Chair	Fabien Clermidy, CEA-Leti, FR
Co-Chair	Walter Weber, Namlab, DE

4.5.1 17:00 – 17:30	3T-TFET bitcell based TFET-CMOS Hybrid SRAM design for Ultra-Low Power Applications Navneet Gupta, Adam Makosiej, Andrei Vladimirescu, Amara Amara and Costin Anghel
4.5.2 17:30 – 18:00	Design of Latches and Flip-Flops using Emerging Tunneling Devices Xunzhao Yin, Behnam Sedighi, Michael Niemier and X. Sharon Hu
4.5.3 18:00 – 17:00	MASC: Ultra-Low Energy Multiple-Access Single-Charge TCAM for Approximate Computing Mohsen Imani, Shruti Patil and Tajana S. Rosing

Session Title	Managing Muli-Core and Flash Memory
Session Code / Room	4.6 / Konferenz 4
Date / Time	Tuesday, 15 March 2016 / 17:00 – 18:30
Chair	Akash Kumar, Technische Universität Dresden, DE
Co-Chair	Olivier Sentiyes, INRIA, FR

4.6.1 17:00 – 17:30	Distributed Fair Scheduling for Many-Cores Anuj Pathania, Vanchinathan Venkataramani, Muhammad Shafique, Tulika Mitra and Jörg Henkel
4.6.2 17:30 – 18:00	Keep It Slow and in Time: Online DVFS with Hard Real-Time Workloads Kai Lampka and Björn Forsberg
4.6.3 18:00 – 18:30	Exploiting Process Variation for Retention Induced Refresh Minimization on Flash Memory Yejia Di, Liang Shi, Kaijie Wu and Chun Jason Xue

Session Title	Modeling of Devices and Mixed-Signal Circuits
Session Code / Room	4.7 / Konferenz 5
Date / Time	Tuesday, 15 March 2016 / 17:00 – 18:30
Chair	Nuno Horta, Instituto de Telecomunicacoes, PT
Co-Chair	Jaijeet Roychowdhury, UC Berkeley, US

4.7.1 17:00 – 17:30	Accurate Synthesis of Integrated RF Passive Components Using Surrogate Models F. Passos, R. González-Echevarría, E. Roca, R. Castro-López and F. V. Fernández
4.7.2 17:30 – 18:00	Implementation and Quality Testing for Compact Models Implemented in Verilog-A Anindya Mukherjee, Andreas Pawlak, Michael Schroter, Didier Celi and Zoltan Huszka
4.7.3 18:00 – 18:30	Multi-Harmonic Nonlinear Modeling of Low-power PWM DC-DC Converters Operating in CCM and DCM Ya Wang, Di Gao, Dani A. Tannir and Peng Li

Session Title	SPECIAL DAY Hot Topic: Building Confidence in Advanced Driver Assistance Systems
Session Code / Room	5.1 / Saal 2
Date / Time	Wednesday, 16 March 2016 / 08:30 – 10:00
Organiser	Samarjit Chakraborty, Technische Universität München (TUM), DE Wolfgang Ecker, Infineon Technologies, DE
Chair	Sebastian Steinhorst, TUM CREATE, SG
Co-Chair	Kai Lampka, Uppsala University, SE

5.1.1 08:30 – 09:00	Availability and Interpretability of Optimal Control for Criticality Estimation in Vehicle Active Safety Stephan Herrmann and Wolfgang Utschick
5.1.2 09:00 – 10:00	Certification Issues in Automotive Driver Assistance Systems Udo Steininger
5.1.3 09:30 – 10:00	Deep Learning in Advanced Driver Assistance Systems Qing Rao

Session Title	Hot Topic: In-memory Computing: Status and Trends
Session Code / Room	5.2 / Konferenz 6
Date / Time	Wednesday, 16 March 2016 / 08:30 – 10:00
Organiser	Pierre-Emmanuel Gaillardon, University of Utah, Salt Lake City, US
Chair	Ian O’Connor, Institute des Nanotechnologies de Lyon, Ecully, FR
Co-Chair	Michael Niemier, University of Notre Dame, South Bend, US

5.2.1 08:30 – 08:52	Software and System Co-Optimization in the ERA of Heterogeneous Computing Ruchir Puri
5.2.2 08:52 – 09:14	Fading Memory Effects in a Memristor for Cellular Nanoscale Network Applications A. Ascoli, R. Tetzlaff, L. O. Chua, J. P. Strachan and R. S. Williams
5.2.3 09:14 – 09:36	Digital Memcomputing Machines Massimiliano Di Ventra and Fabio L. Traversa
5.2.4 09:36 – 10:00	The Programmable Logic-in-Memory (PLiM) Computer Pierre-Emmanuel Gaillardon, Luca Amarú, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay and Giovanni De Micheli

Session Title	Physical Attacks and Countermeasures
Session Code / Room	5.3 / Konferenz 1
Date / Time	Wednesday, 16 March 2016 / 08:30 – 10:00
Chair	Assia Tria, CEA-Leti, FR
Co-Chair	Francesco Regazzoni, ALaRI, CH

5.3.1 08:30 – 09:00	Oracle-Guided Incremental SAT Solving to Reverse Engineer Camouflaged Logic Circuits Duo Liu, Cunxi Yu, Xiangyu Zhang and Daniel Holcomb
5.3.2 09:00 – 09:30	A Fully-Digital EM Pulse Detector David El-Baze, Jean-Baptiste Rigaud and Philippe Maurine
5.3.3 09:30 – 10:00	On the Development of a New Countermeasure Based on a Laser Attack RTL Fault Model Charalampos Ananiadis, Athanasios Papadimitriou, David Hély, Vincent Beroulle, Paolo Maistri and Régis Leveugle

Session Title	Architectural-level Low-power Design
Session Code / Room	5.4 / Konferenz 2
Date / Time	Wednesday, 16 March 2016 / 08:30 – 10:00
Chair	Alberto Macii, Politecnico di Torino, IT
Co-Chair	Pascal Vivet, CEA LETI, FR

5.4.1 08:30 – 09:00	Multi-Story Power Distribution Networks for GPUs Qixiang Zhang, Liangzhen Lai, Mark Gottscho and Puneet Gupta
5.4.2 09:00 – 09:30	Energy-Efficient Cache Memories using a Dual-V t 4T SRAM Cell with Read-Assist Techniques Alireza Shafaei and Massoud Pedram
5.4.3 09:30 – 10:00	Learning-Based Dynamic Reliability Management For Dark Silicon Processor Considering EM Effects Taeyoung Kim, Xin Huang, Hai-Bao Chen, Valeriy Sukharev and Sheldon X.-D. Tan

Session Title	Alternative Computing Models
Session Code / Room	5.5 / Konferenz 3
Date / Time	Wednesday, 16 March 2016 / 08:30 – 10:00
Chair	Yiyu Shi, University of Notre Dame, US
Co-Chair	Sébastien Le Beux, Ecole Centrale de Lyon, FR

5.5.1 08:30 – 09:00	MNSIM: Simulation Platform for Memristor-based Neuromorphic Computing System Lixue Xia, Boxun Li, Tianqi Tang, Peng Gu, Xiling Yin, Wenqin Huangfu, Pai-Yu Chen, Shimeng Yu, Yu Cao, Yu Wang, Yuan Xie and Huazhong Yang
5.5.2 09:00 – 09:30	Conditional Deep Learning for Energy-Efficient and Enhanced Pattern Recognition Priyadarshini Panda, Abhronil Sengupta and Kaushik Roy
5.5.3 09:30 – 10:00	Probabilistic Error Models for Machine Learning Kernels Implemented on Stochastic Nanoscale Fabrics Sai Zhang and Naresh R. Shanbhag

Session Title	Efficient System Modeling with SystemC
Session Code / Room	5.6 / Konferenz 4
Date / Time	Wednesday, 16 March 2016 / 08:30 – 10:00
Chair	Gunar Schirner, Northeastern University, US
Co-Chair	Christian Haubelt, University of Rostock, DE

5.6.1 08:30 – 09:00	A New Parallel SystemC Kernel Leveraging Manycore Architectures Nicolas Ventroux and Tanguy Sassolas
5.6.2 09:00 – 09:30	SystemC-Link: Parallel SystemC Simulation using Time-Decoupled Segments Jan Henrik Weinstock, Rainer Leupers, Gerd Ascheid, Dietmar Petras and Andreas Hoffmann
5.6.3 09:30 – 10:00	Orthogonal Signal Modeling and Operational Computation of AMS Circuits for Fast and Accurate System Simulation Leandro Gil and Martin Radetzki

Session Title	RF, Power Converters, and ADC: Innovative Design and Test Solutions
Session Code / Room	5.7 / Konferenz 5
Date / Time	Wednesday, 16 March 2016 / 08:30 – 10:00
Chair	Marie-Minerve Louerat, Université Pierre & Marie Curie, (UPMC - Paris 6), FR
Co-Chair	Christoph Grimm, University of Kaiserslautern, DE

5.7.1 08:30 – 09:00	Built-in Test of Millimeter-Wave Circuits Based on Non-Intrusive Sensors Athanasios Dimakos, Haralampos-G. Stratigopoulos, Alexandre Siligaris, Salvador Mir and Emeric De Foucauld
5.7.2 09:00 – 09:30	Adaptive Delay Monitoring for Wide Voltage-Range Operation Jongho Kim, Gunhee Lee, Kiyoung Choi, Yonghwan Kim, Wook Kim, Kyungtae Do and Jungyun Choi
5.7.3 09:30 – 10:00	Analytical Design Optimization of Sub-ranging ADC Based on Stochastic Comparator Md. Maruf Hossain, Tetsuya Iizuka, Toru Nakura and Kunihiro Asada

Session Title	Interactive Presentations
Session Code / Room	IP2
Date / Time	Wednesday, 16 March 2016 / 10:00 – 10:30

IP2-1	Analyzing the Impact of Injected Sensor Data on an Advanced Driver Assistance System using the OP₂ TIMUS Prototyping Platform Alexander Stühring, Günter Ehmen and Sibylle Fröschle
IP2-2	Hardware Trojans in Incompletely Specified On-chip Bus Systems Nicole Fern, Ismail San, Çetin Kaya Koç and Kwang-Ting (Tim) Cheng
IP2-3	Workload-aware Power Optimization Strategy for Asymmetric Multiprocessors E. Del Sozzo, G. C. Durelli, E. M. G. Trainiti, A. Miele, M. D. Santambrogio and C. Bolchini
IP2-4	The Slowdown or Race-to-idle Question: Workload-Aware Energy Optimization of SMT Multicore Platforms under Process Variation Anup Das, Geoff V. Merrett and Bashir M. Al-Hashimi
IP2-5	Towards General Purpose Computations on Low-End Mobile GPUs Matina Maria Trompouki and Leonidas Kosmidis
IP2-6	Estimating Delay Differences of Arbiter PUFs Using Silicon Data S. V. Sandeep Avvaru, Chen Zhou, Saroj Satapathy, Yingjie Lao, Chris H. Kim and Keshab K. Parhi
IP2-7	On the Use of Forward Body Biasing to Decrease the Repeatability of Laser-Induced Faults Marc Lacruche, Noemie Beringuier-Boher, Jean-Max Dutertre, Jean-Baptiste Rigaud and Edith Kussener
IP2-8	Sequential Analysis Driven Reset Optimization to Improve Power, Area and Routability Srihari Yechangunja, Raj Shekhar, Mohit Kumar, Nikhil Tripathi, Abhishek Mittal, Abhishek Ranjan, Jianfeng Liu, Minyoung Mo, Kyungtae Do, Jung Yun Choi and SungHo Park
IP2-9	Efficient Global Optimization of MEMS Based on Surrogate Model Assisted Evolutionary Algorithm Bo Liua and Anna Nikolaeva
IP2-10	Efficient Monitoring of Loose-Ordering Properties for SystemC/TLM Yuliia Romenska and Florence Maraninchi
IP2-11	Testable Design of Repeaterless Low Swing On-Chip Interconnect K. Naveen and Dinesh K. Sharma
IP2-12	ll-digital Hybrid-control Buck Converter for Integrated Voltage Regulator Applications Ta-Tung Yen, Bin Yu, Visvesh S. Sathe

Session Title	SPECIAL DAY Hot Topic: Formal Methods for Automotive Software
Session Code / Room	6.1 / Saal 2
Date / Time	Wednesday, 16 March 2016 / 11:00 – 12:30
Chair	Marc Geilen, Eindhoven University of Technology, NL
Co-Chair	Wolfgang Ecker, Infineon Technologies, DE

6.1.1 11:00 – 11:30	Requirements Engineering for Software-Intensive Automotive Embedded Systems Manfred Broy
6.1.2 11:30 – 12:00	Formal Specification and Verification of Automotive Software in Practice Ravindra Metta
6.1.3 12:00 – 12:30	Timing Analysis of Automotive Architectures and Software Nicolas Navet

Session Title	Panel: Looking Backwards and Forwards
Session Code / Room	6.2 / Konferenz 6
Date / Time	Wednesday, 16 March 2016 / 11:00 – 12:30
Organiser	Marco Casale-Rossi, Synopsys, US
Chair	Marco Casale-Rossi, Synopsys, US
Co-Chair	Giovanni De Micheli, EPFL, CH

6.2.1 11:00 – 12:30	Panel: Looking Backwards and Forwards Marco Casale-Rossi, Giovanni De Micheli, Antun Domic, Enrico Macii, Domenico Rossi and Joe Sawicki
6.2.2 11:00 – 12:30	Panelist Enrico Macii
6.2.3 11:00 – 12:30	Panelist Antun Domic
6.2.4 11:00 – 12:30	Panelist Domenico Rossi
6.2.5 11:00 – 12:30	Panelist Joseph Sawicki
6.2.6 11:00 – 12:30	Moderator Giovanni De Micheli

Session Title	Anti-aging and Error protection using Checkpointing and DVFS
Session Code / Room	6.3 / Konferenz 1
Date / Time	Wednesday, 16 March 2016 / 11:00 – 12:30
Chair	Antonio Rosario Miele, Polimi, IT
Co-Chair	Jose L. Ayala, Complutense University of Madrid, ES

6.3.1 11:00 – 11:30	Aging-Aware Voltage Scaling Victor M. van Santen, Hussam Amrouch, Narendra Parihar, Souvik Mahapatra and Jörg Henkel
6.3.2 11:30 – 12:00	RECORD: Reducing Register Traffic for Checkpointing in Embedded Processors Tuo Li, Jude Angelo Ambrose and Sri Parameswaran
6.3.3 12:00 – 12:15	Error Resilience and Energy Efficiency: An LDPC Decoder Design Study Philipp Schläfer, Chu-Hsiang Huang, Clayton Schoeny, Christian Weis, Yao Li, Norbert Wehn and Lara Dolecek
6.3.4 12:15 – 12:30	Runtime Interval Optimization and Dependable Performance for Application-Level Checkpointing Apostolos Kokolis, Alexandros Mavrogiannis, Dimitrios Rodopoulos, Christos Strydis and Dimitrios Soudris

Session Title	Power Modeling and Power Aware Synthesis
Session Code / Room	6.4 / Konferenz 2
Date / Time	Wednesday, 16 March 2016 / 11:00 – 12:30
Chair	Alberto Garcia Ortiz, University of Bremen, DE
Co-Chair	Qi Zhu, UCR, US

6.4.1 11:00 – 11:30	A Systematic Approach to Automated Construction of Power Emulation Models Benjamin A. Bjørnseth, Asbjørn Djupdal and Lasse Natvig
6.4.2 11:30 – 12:00	Automatic Generation of Power State Machines through Dynamic Mining of Temporal Assertions Alessandro Danese, Graziano Pravadelli and Ivan Zandonà
6.4.3 12:00 – 12:30	Approximation through Logic Isolation for the Design of Quality Configurable Circuits Shubham Jain, Swagath Venkataramani and Anand Raghunathan

Session Title	Biochips
Session Code / Room	6.5 / Konferenz 3
Date / Time	Wednesday, 16 March 2016 / 11:00 – 12:30
Chair	Robert Wille, JKU, AT
Co-Chair	Ian O’Connor, Ecole Centrale de Lyon, FR

6.5.1 11:00 – 11:30	Architecture Synthesis for Cost-Constrained Fault-Tolerant Flow-based Biochips Morten Chabert Eskesen, Paul Pop and Seetal Potluri
6.5.2 11:30 – 12:00	Sieve-valve-aware Synthesis of Flow-based Microfluidic Biochips Considering Specific Biological Execution Limitations Mengchu Li, Tsun-Ming Tseng, Bing Li, Tsung-Yi Ho and Ulf Schlichtmann
6.5.3 12:00 – 12:30	Integrated and Real-Time Quantitative Analysis Using Cyberphysical Digital-Microfluidic Biochips Mohamed Ibrahim, Krishnendu Chakrabarty and Kristin Scott

Session Title	Modelling and Control of Cyber-Physical Systems
Session Code / Room	6.6 / Konferenz 4
Date / Time	Wednesday, 16 March 2016 / 11:00 – 12:30
Chair	Donatella Sciuto, Politecnico di Milano, IT
Co-Chair	Paul Pop, Technical University of Denmark, DK

6.6.1 11:00 – 11:30	Self-Triggered Controllers and Hard Real-Time Guarantees Amir Aminifar, Paulo Tabuada, Petru Eles and Zebo Peng
6.6.2 11:30 – 12:00	A Spatio-Temporal Fractal Model for a CPS Approach to Brain-Machine-Body Interfaces Yuankun Xue, Saul Rodriguez and Paul Bogdan
6.6.3 12:00 – 12:15	Modular Code Generation for Emulating the Electrical Conduction System of the Human Heart Nathan Allen, Sidharta Andalam, Partha Roop, Avinash Malik, Mark Trew and Nitish Patel
6.6.4 12:15 – 12:30	Resource Utilization and Quality-of-Control Trade-off for a Composable Platform Juan Valencia, E.P. (Eelco) van Horssen, Dip Goswami, W. P. M. H. (Maurice) Heemels and Kees Goossens

Session Title	Fault Tolerant Systems and Methods
Session Code / Room	6.7 / Konferenz 5
Date / Time	Wednesday, 16 March 2016 / 11:00 – 12:30
Chair	Viacheslav Izosimov, Semcon Sweden AB, SE
Co-Chair	Zebo Peng, Linköping University, SE

6.7.1 11:00 – 11:30	Inexact Designs for Approximate Low Power Addition by Cell Replacement Haider A. F. Almurib, T. Nandha Kumar and Fabrizio Lombardi
6.7.2 11:30 – 12:00	A General Approach for Highly Defect Tolerant Parallel Prefix Adder Design Soumya Banerjee and Wenjing Rao
6.7.3 12:00 – 12:30	Inverters’ Self-Checking Monitors for Reliable Photovoltaic Systems M. Omaña, A. Fiore and C. Metra

Session	Lunch Time Keynote Session
Session Code / Room	7.0
Date / Time	Wednesday, 16 March 2016 / 14:00 – 14:30
Chair	Luca Fanucci, University of Pisa, IT
Co-Chair	Wolfgang Ecker, Infineon Technologies, DE

7.0.1
14:00 – 14:30

[Keynote] The Car of the Future will reinvent personal mobility
Patrick Leteinturier

Session Title	SPECIAL DAY Panel: Which EDA Solutions can the Automotive Domain Reuse? Very Few or All?
Session Code / Room	7.1 / Saal 2
Date / Time	Wednesday, 16 March 2016 / 14:30 – 16:00
Chair	Adam Morawiec, European Chips & Systems Design Initiative (ESCI), FR

7.1.2 14:30 – 16:00	Panelist Rainer Kress
7.1.3 14:30 – 16:00	Panelist Gabriele Ernst
7.1.4 14:30 – 16:00	Panelist Jean-Marie Saint-Paul
7.1.5 14:30 – 16:00	Panelist Silvano Motto
7.1.6 14:30 – 16:00	Panelist Christoph Störmer
7.1.1 14:30 – 16:00	Moderator Oliver Bringmann

Session Title	EU Projects Special Session: Energy Efficiency drives Design
Session Code / Room	7.2 / Konferenz 6
Date / Time	Wednesday, 16 March 2016 / 14:30 – 16:00
Organiser	Roberto Giorgi, University of Siena, IT
Chair	Martin Schoeberl, Technical University of Denmark, DK
Co-Chair	Roberto Giorgi, University of Siena, IT

7.2.1 14:30 – 14:45	EUROSERVER: Share-Anything Scale-Out Micro-Server Design Manolis Marazakis, John Goodacre, Didier Fuin, Paul Carpenter, John Thomson, Emil Matus, Antimo Bruno, Per Stenstrom, Jerome Martin, Yves Durand and Isabelle Dor
7.2.2 14:45 – 15:00	Energy Minimization at All Layers of the Data Center: The ParaDIME Project Oscar Palomar, Santhosh Rethinagiri, Gulay Yalcin, Ruben Titos-Gil, Pablo Prieto, Emma Torrella, Osman Unsal, Adrian Cristal, Pascal Felber, Anita Sobe, Yaroslav Hayduk, Mascha Kurpicz, Christof Fetzer, Thomas Knauth, Malte Schneegaß, Jens Struckmeier and Dragomir Milojevic
7.2.3 15:00 – 15:15	Rack-scale Disaggregated Cloud Data Centers: The dReDBox Project Vision K. Katrinis, D. Syrivelis, D. Pnevmatikatos, G. Zervas, D. Theodoropoulos, I. Koutsopoulos, K. Hasharoni, D. Raho, C. Pinto, F. Espina, S. Lopez-Buedo, Q. Chen, M. Nemirovsky, D. Roca, H. Klos and T. Berends
7.2.4 15:15 – 15:30	ECOSCALE: Reconfigurable Computing and Runtime System for Future Exascale Systems Iakovos Mavroidis, Ioannis Papaefstathiou, Luciano Lavagno, Dimitrios S. Nikolopoulos, Dirk Koch, John Goodacre, Ioannis Sourdis, Vassilis Papaefstathiou, Marcello Coppola and Manuel Palomino
7.2.5 15:30 – 15:45	Enabling HPC for QoS-sensitive Applications: The MANGO Approach José Flich, Giovanni Agosta, Philipp Ampletzerz, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinarić, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero and Davide Zoni
7.2.6 15:45 – 16:00	AutoTuning and Adaptivity appRoach for Energy Efficient eXascale HPC Systems: The ANTAREX Approach Cristina Silvano, Giovanni Agosta, Andrea Bartolini, Andrea R. Beccari, Luca Benini, João Bispo, Radim Cmar, João M. P. Cardoso, Carlo Cavazzoni, Jan Martinovic, Gianluca Palermo, Martin Palkovic, Pedro Pinto, Erven Rohou, Nico Sanna and Katerina Slaninová

Session Title	Low Power Devices and Methods for Healthcare and Assisted Living
Session Code / Room	7.3 / Konferenz 1
Date / Time	Wednesday, 16 March 2016 / 14:30 – 16:00
Chair	José M. Moya, Technical University of Madrid, ES
Co-Chair	Giovanni Ansaloni, University of Lugano, CH

7.3.1 14:30 – 15:00	A Digital Processor Architecture for Combined EEG/EMG Falling Risk Prediction V. F. Annese, M. Crepaldi, D. Demarchi and D. De Venuto
7.3.2 15:00 – 15:30	Distributed-neuron-network based Machine Learning on Smart-gateway Network Towards Real-time Indoor Data Analytics Hantao Huang, Yuehua Cai and Hao Yu
7.3.3 15:30 – 15:45	Touch-Based System for Beat-to-Beat Impedance Cardiogram Acquisition and Hemodynamic Parameters Estimation Dionisije Sopic, Srinivasan Murali, Francisco Rincón and David Atienza
7.3.4 15:45 – 16:00	Quantifying the Benefits of Compressed Sensing on a WBSN-based Real-Time Biosignal Monitor Daniele Bortolotti, Bojan Milosevic, Andrea Bartoliniy, Elisabetta Farellaand Luca Benini

Session Title	System-Level Synthesis
Session Code / Room	7.4 / Konferenz 2
Date / Time	Wednesday, 16 March 2016 / 14:30 – 16:00
Chair	Cathal McCabe, Xilinx, Inc. Ireland, IE
Co-Chair	Yuichi Nakamura, NEC Japan, JP

7.4.1 14:30 – 15:00	System Level Synthesis for Virtual Memory Enabled Hardware Threads Nicolas Estibals, Gaël Deest, Ali Hassan El Moussawi and Steven Derrien
7.4.2 15:00 – 15:30	Composable, Parameterizable Templates for High-Level Synthesis Janarbek Matai, Dajung Lee, Alric Althoff and Ryan Kastner
7.4.3 15:30 – 16:00	Leveraging Power Spectral Density for Scalable System-Level Accuracy Evaluation Benjamin Barrois, Karthick Parashar and Olivier Sentieys

Session Title	Emerging Memory Architectures
Session Code / Room	7.5 / Konferenz 3
Date / Time	Wednesday, 16 March 2016 / 14:30 – 16:00
Chair	Amara Amara, ISEP, FR
Co-Chair	Fabian Oboril, Karlsruhe Institute of Technology, DE

7.5.1 14:30 – 15:00	Leader: Accelerating ReRAM-based Main Memory by Leveraging Access Latency Discrepancy in Crossbar Arrays Hang Zhang, Nong Xiao, Fang Liu and Zhiguang Chen
7.5.2 15:00 – 15:30	Sliding Basket: An Adaptive ECC Scheme for Runtime Write Failure Suppression of STT-RAM Cache* Xue Wang, Mengjie Mao, Enes Eken, Wujie Wen, Hai Li and Yiran Chen
7.5.3 15:30 – 16:00	Exploiting More Parallelism from Write Operations on PCM Zheng Li, Fang Wang, Yu Hua, Wei Tong, Jingning Liu, Yu Chen and Dan Feng

Session Title	Statistical and Symbolic Techniques for the Analysis and Testing of Embedded Software
Session Code / Room	7.6 / Konferenz 4
Date / Time	Wednesday, 16 March 2016 / 14:30 – 16:00
Chair	Jian-Jia Chen, Technische Universität Dortmund, DE
Co-Chair	Petru Eles, Linköping University, SE

7.6.1 14:30 – 15:00	Dynamic Partitioning Strategy to Enhance Symbolic Execution Brendan A. Marcellino and Michael S. Hsiao
7.6.2 15:00 – 15:30	Quantitative Timing Analysis of UML Activity Diagrams Using Statistical Model Checking Fan Gu, Xinqian Zhang, Mingsong Chen, Daniel Große and Rolf Drechsler
7.6.3 15:30 – 16:00	Integrating Symbolic and Statistical Methods for Testing Intelligent Systems Applications to Machine Learning and Computer Vision Arvind Ramanathan, Laura L. Pullum, Faraz Hussain, Dwaipayan Chakrabarty and Sumit Kumar Jha

Session Title	Aging Mitigation to Improve System Robustness
Session Code / Room	7.7 / Konferenz 5
Date / Time	Wednesday, 16 March 2016 / 14:30 – 16:00
Chair	Maria Michael, University of Cyprus, CY
Co-Chair	Carles Hernandez, Barcellona Supercomputer Center, ES

7.7.1 14:30 – 15:00	Path Selection and Sensor Insertion Flow for Age Monitoring in FPGAs Mohammad Ebrahimi, Zana Ghaderi, Eli Bozorgzadeh and Zain Navabi
7.7.2 15:00 – 15:30	Design and Evaluation of Reliability-oriented Task Re-Mapping in MOSoCs using Time-Series Analysis of Intermittent Faults Siva Satyendra Sahoo, Akash Kumar and Bharadwaj Veeravalli
7.7.3 15:30 – 16:00	Lifetime-aware Load Distribution Policies in Multi-core Systems: An In-depth Analysis Cristiana Bolchini, Luca Cassano and Antonio Miele

Session Title	Interactive Presentations
Session Code / Room	IP3
Date / Time	Wednesday, 16 March 2016 / 16:00 – 16:30

IP3-1	A Flexible Inexact TMR Technique for SRAM-based FPGAs Shyamsundar Venkataraman, Rui Santos and Akash Kumar
IP3-2	Accurate Verification of RC Power Grids Mohammad Fawaz and Farid N. Najm
IP3-3	Security-Aware Development of Cyber-Physical Systems Illustrated with Automotive Case Study Viacheslav Izosimov, Alexandros Asvestopoulos, Oscar Blomkvist and Martin Törngren
IP3-4	Online Heuristic for the Multi-objective Generalized Traveling Salesman Problem Joost van Pinxten, Marc Geilen, Twan Basten, Umar Waqas and Lou Somers
IP3-5	Towards Low Overhead Control Flow Checking Using Regular Structured Control Zhiqi Zhu and Joseph Callenes-Sloan
IP3-6	Emulation-Based Hierarchical Fault-Injection Framework for Coarse-to-Fine Vulnerability Analysis of Hardware-Accelerated Approximate Algorithms Ioannis Chadjiminas, Ioannis Savva, Christos Kyrkou, Maria K. Michael and Theocharis Theocharides
IP3-7	Technology Transfer in Computing Systems: The TETRACOM Approach Rainer Leupers
IP3-8	Energy vs. Reliability Trade-offs Exploration in Biomedical Ultra-Low Power Devices Loris Duch, P. Garcia del Valle, Shrikanth Ganapathy, Andreas Burg and David Atienza
IP3-9	A Machine Learning Approach for Medication Adherence Monitoring Using Body-Worn Sensors Niloofar Hezarjaribi, Ramin Fallahzadeh and Hassan Ghasemzadeh
IP3-10	Requirements-Centric Closed-Loop Validation of Implantable Cardiac Devices Weiwei Ai, Nitish Patel and Partha Roop
IP3-11	Low Normalized Energy Derivation Asynchronous Circuit Synthesis Flow through Fork-Join Slack Matching for Cryptographic Applications Nan Liu, Kwen-Siong Chong, Weng-Geng Ho, Bah-Hwee Gwee and Joseph S. Chang
IP3-12	A Lifetime-Aware Runtime Mapping Approach for Many-core Systems in the Dark Silicon Era Mohammad-Hashem Haghbayan, Antonio Miele, Amir M. Rahmani, Pasi Liljeberg and Hannu Tenhunen

Session Title	SPECIAL DAY Hot Topic: Connectivity in the Automotive Domain: From Micro to Macro
Session Code / Room	8.1 / Saal 2
Date / Time	Wednesday, 16 March 2016 / 17:00 – 18:30
Chair	Henk Corporaal, Eindhoven University of Technology, NL
Co-Chair	Samarjit Chakraborty, Technische Universität München (TUM), DE

8.1.1 17:00 – 17:30	Automotive V2X on Phones: Enabling Next-generation Mobile ITS Apps Jason H. Gao and Li-Shiuan Peh
8.1.2 17:30 – 18:00	EDA for automotive cabling Thomas Heurung, Mentor, DE
8.1.3 18:00 – 18:30	Deterministic Ethernet in Automotive Applications Astrit Ademaj, TTTech Computertechnik AG, AT

Session Title	EU Projects Special Session: Towards Better EU-projects – Success Stories
Session Code / Room	8.2 / Konferenz 6
Date / Time	Wednesday, 16 March 2016 / 17:00 – 18:30
Organiser	Roberto Giorgi, University of Siena, IT
Chair	Cristina Silvano, Politecnico of Milan, IT
Co-Chair	Roberto Giorgi, University of Siena, IT

8.2.1 17:00 – 17:15	Collective Knowledge: Towards R&D Sustainability Grigori Fursin, Anton Lokhmotov and Ed Plowman
8.2.2 17:15 – 17:30	Lessons Learned from the EU Project T-CREST Martin Schoeberl
8.2.3 17:30 – 17:45	MULTI-POS: Marie Curie Network in Multi-technology Positioning Jari Nurmi and Elena-Simona Lohan
8.2.4 17:45 – 18:00	Program Transformations in the POLCA Project Jan Kuper, Lutz Schubert, Kilian Kempf, Colin Glass, Daniel Rubio Bonilla and Manuel Carro
8.2.5 18:00 – 18:15	Computation and Communication Challenges to Deploy Robots in Assisted Living Environments Georgios Keramidas, Christos Antonopoulos, Nikolaos S. Voros, Fynn Schwiegelshohn, Philipp Wehner, Jens Rettkowski, Diana Göhringer, Michael Hübner, Stasinos Konstantopoulos, Theodore Giannakopoulos, Vangelis Karkaletsis and Vaggelis Mariatos
8.2.6 18:15 – 18:30	ATHENIS_3D: Automotive Tested High-voltage and Embedded Non-volatile Integrated SoC Platform with 3D Technology E. Wachmann, S. Saponara, C. Zambelli, P. Tisserand, J. Charbonnier, T. Erlbacher, S. Gruenler, C. Hartler, J. Siegert, P. Chassard, D. M. Ton, L. Ferrari and L. Fanucci

Session Title	Hot Topic: Managing Heterogeneous Computing Resources at Runtime
Session Code / Room	8.3 / Konferenz 1
Date / Time	Wednesday, 16 March 2016 / 17:00 – 18:30
Organisers	Christian Plessl, University of Paderborn, DE David Andrews, University of Arkansas, US
Chair	Daniel Ziener, Hamburg University of Technology, DE
Co-Chair	José L. Ayala, Complutense University of Madrid, ES

8.3.1 17:00 – 17:30	Run Time Interpretation for Creating Custom Accelerators Sen Ma, Zeyad Aklah and David Andrews
8.3.2 17:30 – 18:00	A Self-Adaptive Approach to Efficiently Manage Energy and Performance in Tomorrow’s Heterogeneous Computing Systems E. M. G. Trainiti, G. C. Durelli, A. Miele, C. Bolchini and M. D. Santambrogio
8.3.3 18:00 – 18:30	Performance-Centric Scheduling with Task Migration for a Heterogeneous Compute Node in the Data Center Achim Lösch, Tobias Beisel, Tobias Kenter, Christian Plessl and Marco Platzner

Session Title	Advanced Methods in High-Level Design
Session Code / Room	8.4 / Konferenz 2
Date / Time	Wednesday, 16 March 2016 / 17:00 – 18:30
Chair	Fabian Oboril, KIT Germany, DE
Co-Chair	Luciano Lavagno, Politecnico di Torino, IT

8.4.1 17:00 – 17:30	Adaptive Threshold Non-Pareto Elimination: Re-thinking Machine Learning for System Level Design Space Exploration on FPGAs Pingfan Meng, Alric Althoff, Quentin Gautier and Ryan Kastner
8.4.2 17:30 – 18:00	Monitoring of MTL Specifications With IBM’s Spiking-Neuron Model Konstantin Selyunin, Thang Nguyen, Ezio Bartocci, Dejan Nickovic and Radu Grosu
8.4.3 18:00 – 18:30	Formal Probabilistic Analysis of Distributed Resource Management Schemes in On-Chip Systems Shafaq Iqtedar, Osman Hasan, Muhammad Shafique and Jörg Henkel

Session Title	Non-volatile Memory Design Methodologies
Session Code / Room	8.5 / Konferenz 3
Date / Time	Wednesday, 16 March 2016 / 17:00 – 18:30
Chair	Michael Huebner, RUB, DE
Co-Chair	Michael Niemier, University of Notre Dame, US

8.5.1 17:00 – 17:30	An Operating System Level Data Migration Scheme in Hybrid DRAM-NVM Memory Architecture Reza Salkhordeh and Hossein Asadi
8.5.2 17:30 – 18:00	Unified DRAM and NVM Hybrid Buffer Cache Architecture for Reducing Journaling Overhead Zhiyong Zhang, Lei Ju and Zhiping Jia
8.5.3 18:00 – 18:30	Fast Logic Synthesis for RRAM-based In-Memory Computing using Majority-Inverter Graphs Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon and Rolf Drechsler

Session Title	Dataflow Modeling and Natural Language Processing
Session Code / Room	8.6 / Konferenz 4
Date / Time	Wednesday, 16 March 2016 / 17:00 – 18:30
Chair	Dominique Borrione, Laboratoire TIMA, FR
Co-Chair	Marc Geilen, Eindhoven University of Technology, NL

8.6.1 17:00 – 17:30	Exploiting Resource-constrained Parallelism in Hard Real-Time Streaming Applications Jelena Spasic, Di Liu and Todor Stefanov
8.6.2 17:30 – 18:00	Transaction Parameterized Dataflow: A Model for Context-Dependent Streaming Applications Xuan Khanh Do, Stephane Louise and Albert Cohen
8.6.3 18:00 – 18:30	GLAsT: Learning Formal Grammars to Translate Natural Language Specifications into Hardware Assertions Christopher B. Harris and Ian G. Harris

Session Title	Test Methods Handling Unkowns, 2.50 Integration and Realistic Memory Defects
Session Code / Room	8.7 / Konferenz 5
Date / Time	Wednesday, 16 March 2016 / 17:00 – 18:30
Chair	Friedrich Hapke, Mentor Graphics Hamburg, DE

8.7.1 17:00 – 17:30	Accurate CEGAR-based ATPG in Presence of Unknown Values for Large Industrial Designs Karsten Scheibler, Dominik Erb and Bernd Becker
8.7.2 17:30 – 18:00	Pre-Bond Testing of the Silicon Interposer in 2.5D ICs Ran Wang, Zipeng Li, Sukeshwar Kannan and Krishnendu Chakrabarty
8.7.3 18:00 – 18:30	Improving SRAM Test Quality by Leveraging Self-timed Circuits Josef Kinseher, Leonardo B. Zordan, Ilia Polian and Andreas Leininger

Session Title	SPECIAL DAY Embedded Tutorial: Embedded Systems Security
Session Code / Room	9.1 / Saal 2
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Chair	Matthias Schunter, Intel, DE
Co-Chair	Wieland Fischer, Infineon Technologies, DE

9.1.1
08:30 – 10:00

Software Security: Vulnerabilities and Countermeasures for Two Attacker Models
Frank Piessens and Ingrid Verbauwhede

Session Title	Managing the Traffic Jam in NoC
Session Code / Room	9.2 / Konferenz 6
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Chair	Nader Bagherzadeh, University of California Irvine, US
Co-Chair	Massoud Daneshtalab, KTH, SE

9.2.1 08:30 – 09:00	OLITS: An Ohm’s Law-like Traffic Splitting Model Based on Congestion Prediction Gaoming Du, Yanghao Ou, Xiangyang Li, Ping Song, Zhonghai Lu and Minglun Gao
9.2.2 09:00 – 09:30	MCAPI-compliant Hardware Buffer Manager Mechanism to Support Communication in Multi-Core Architectures Thiago Raupp da Rosa, Thomas Mesquida, Romain Lemaire and Fabien Clermidy
9.2.3 09:30 – 10:00	Slack-Based Resource Arbitration for Real-Time Networks-On-Chip Adam Kostrzewa, Selma Saidi and Rolf Ernst

Session Title	Industrial Experiences
Session Code / Room	9.3 / Konferenz 1
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Chair	Norbert Wehn, University of Kaiserslautern, DE
Co-Chair	Stephan Diestelhorst, ARM, US

9.3.1 08:30 – 08:45	Challenges of Using On-Chip Performance Monitors for Process and Environmental Variation Compensation Mahroo Zandrahimi, Zaid Al-Ars, Philippe Debaudand Armand Castillejo
9.3.2 08:45 – 09:00	Study of Workload Impact on BTI HCI Induced Aging of Digital Circuits Ajith Sivadasan, Florian Cacho, Sidi Ahmed Benhassain, Vincent Huard and Lorena Anghel
9.3.3 09:00 – 09:15	Fast Prototyping Platform for Navigation Systems with Sensors Fusion Charly Bechara, Karim Ben Chehida, Mickael Guibert, Renaud Schmit, Maria Lepecq, Laurent Soulier, Thomas Dombek and Yann Leclerc
9.3.4 09:15 – 09:30	Precision Timed Industrial Automation Systems Matthew M. Y. Kuo, Sidharta Andalam and Partha S. Roop
9.3.5 09:30 – 09:45	AUTOSAR-based Communication Coprocessor for Automotive ECUs Ahmed Hamed, Mona Safar, M. Watheq El-Kharashiand Ashraf Salem
9.3.6 09:45 – 10:00	Mantissa-Masking for Energy-Efficient Floating-Point LTE Uplink MIMO Baseband Processing D. Guenther, T. Henriksson, R. Leupers, G. Ascheid

Session Title	Optimization for Logic and Physical Design
Session Code / Room	9.4 / Konferenz 2
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Chair	Valeria Bertacco, Univ. of Michigan, US
Co-Chair	Sven Peyer, IBM, DE

9.4.1 08:30 – 09:00	Optimizing Majority-Inverter Graphs With Functional Hashing Mathias Soeken, Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon and Giovanni De Micheli
9.4.2 09:00 – 09:30	Resource-Aware Functional ECO Patch Generation An-Che Cheng, Iris Hui-Ru Jiang and Jing-Yang Jou
9.4.3 09:30 – 10:00	Simultaneous Slack Matching, Gate Sizing and Repeater Insertion for Asynchronous Circuits Gang Wu and Chris Chu

Session Title	Formal Bit Precise Reasoning
Session Code / Room	9.5 / Konferenz 3
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Chair	Markus Wedler, Synopsys GmbH, DE
Co-Chair	Julien Schmaltz, Eindhoven University of Technology, NL

9.5.1 08:30 – 09:00	Formal Verification of Integer Multipliers by Combining Gröbner Basis with Logic Reduction Amr Sayed-Ahmed, Daniel Große, Ulrich Kühne, Mathias Soeken and Rolf Drechsler
9.5.2 09:00 – 09:30	Root-Cause Analysis for Memory-Locked Errors John Adler, Djordje Maksimovic and Andreas Veneris
9.5.3 09:30 – 10:00	Formal Verification of Clock Domain Crossing using Gate-level Models of Metastable Flip-Flops Ghaith Tarawneh, Andrey Mokhov and Alex Yakovlev

Session Title	Real-Time Scheduling
Session Code / Room	9.6 / Konferenz 4
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Chair	Frank Slomka, Universität Ulm, DE
Co-Chair	Kai Lampka, Uppsala University, SE

9.6.1 08:30 – 09:00	Response-Time Analysis of DAG Tasks under Fixed Priority Scheduling with Limited Preemptions Maria A. Serrano, Alessandra Melani, Marko Bertogna and Eduardo Quinones
9.6.2 09:00 – 09:30	Speed Optimization for Tasks with Two Resources Alessandra Melani, Renato Mancuso, Daniel Cullina, Marco Caccamo and Lothar Thiele
9.6.3 09:30 – 10:00	Self-Suspension Real-Time Tasks under Fixed-Relative-Deadline Fixed-Priority Scheduling Wen-Hung Huang and Jian-Jia Chen

Session Title	Temperature Awareness in Computing Systems
Session Code / Room	9.7 / Konferenz 5
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Chair	Muhammad Shafique, Karlsruhe Institute of Technology, DE
Co-Chair	Marina Zapater, Complutense University of Madrid, ES

9.7.1 08:30 – 09:00	Thermal-aware Dynamic Page Allocation Policy by Future Access Patterns for Hybrid Memory Cube (HMC) Wei-Hen Lo, Kai-zen Liang and TingTing Hwang
9.7.2 09:00 – 09:30	Minimizing Peak Temperature for Pipelined Hard Real-time Systems Long Cheng, Kai Huang, Gang Chen, Biao Hu and Alois Knoll
9.7.3 09:30 – 10:00	Thermal Aware Scheduling and Mapping of Multiphase Applications onto Chip Multiprocessor Aryabartta Sahu

Session Title	Embedded Tutorial: Analog-/Mixed-Signal Verification Methods for AMS Coverage Analysis
Session Code / Room	9.8 / Exhibition Theater
Date / Time	Thursday, 17 March 2016 / 08:30 – 10:00
Organisers	Gregor Nitsche, OFFIS, DE
Chair	Lars Hedrich, Johann Wolfgang Goethe-Universität, DE
Co-Chair	Christoph Grimm, University of Kaiserslautern, DE

9.8.0 08:30 – 10:00	Embedded Tutorial: Analog-/Mixed-Signal Verification Methods for AMS Coverage Analysis Erich Barke, Andreas Fürtig, Georg Gläser, Christoph Grimm, Lars Hedrich, Stefan Heinen, Eckhard Hennig, Hyun-Sek Lukas Lee, Wolfgang Nebel, Gregor Nitsche, Markus Olbrich, Carna Radojicic and Fabian Speicher
9.8.1 08:30 – 09:00	Towards More Dependable Verification Using Symbolic Simulation Carna Radojicic, Christoph Grimm, Fabian Speicher and Stefan Heinen
9.8.2 09:00 – 09:30	Identification of Critical Scenarios in AMS Verification: Methodology for Finding the Safe Operating Area of AMS Systems Georg Gläser, Hyun-Sek Lukas Lee, Markus Olbrich, Erich Barke and Eckhard Hennig
9.8.3 09:30 – 10:00	AMS Leaf-Component Characterization with Contracts and Satisfaction Checking vs. Electronic Circuit Schematics Gregor Nitsche, Andreas Fürtig, Lars Hedrich and Wolfgang Nebel

Session Title	Interactive Presentations
Session Code / Room	IP4
Date / Time	Thursday, 17 March 2016 / 10:00 – 10:30

IP4-1	A q-gram Birthmarking Approach to Predicting Reusable Hardware Kevin Zeng and Peter Athanas
IP4-2	Captopril: Reducing the Pressure of Bit Flips on Hot Locations in Non-Volatile Main Memories Majid Jalili and Hamid Sarbazi-Azad
IP4-3	Handling Complex Dependencies in System Design Mischa Moestl and Rolf Ernst
IP4-4	A Synthesis-Agnostic Behavioral Fault Model for High Gate-Level Fault Coverage Anton Karputkin and Jaan Raik
IP4-6	Combining Graph-based Guidance with Error Effect Simulation for Efficient Safety Analysis Jo Laufenberg, Sebastian Reiter, Alexander Viehl, Oliver Bringmann, Thomas Kropf and Wolfgang Rosenstiel
IP4-7	Packet Security with Path Sensitization for NoCs Travis Boraten and Avinash Karanth Kodi
IP4-8	Synthesis of Approximate Coders for On-chip Interconnects Using Reversible Logic Robert Wille, Oliver Keszocze, Stefan Hillmich, Marcel Walter and Alberto Garcia-Ortiz
IP4-9	Design-Synthesis Co-Optimisation Using Skewed and Tapered Gates Ayan Datta, James D. Warnock, Ankur Shukla, Saurabh Gupta, Yiu. H. Chan, Karthik Mohan and Charudhattan Nagarajan
IP4-10	A Synthesis-Parameter Tuning System for Autonomous Design-Space Exploration Matthew M. Ziegler, Hung-Yi Liu, George Gristede, Bruce Owens, Ricardo Nigaglioni and Luca P. Carloni
IP4-11	Unbounded Safety Verification for Hardware Using Software Analyzers Rajdeep Mukherjee, Peter Schrammel, Daniel Kroening and Tom Melham
IP4-12	Verilog2SMV: A Tool for Word-level Verification Ahmed Irfan, Alessandro Cimatti, Alberto Griggio, Marco Roveri and Roberto Sebastiani
IP4-13	Towards Formal Verification of Real-World SystemC TLM Peripheral Models — A Case Study Hoang M. Le, Vladimir Herdt, Daniel Große and Rolf Drechsler
IP4-14	Frequency Scheduling For Resilient Chip Multi-Processors Operating at Near Threshold Voltage Ying Wang, Huawei Li and Xiaowei Li
IP4-15	A Low Overhead Error Confinement Method based on Application Statistical Characteristics Zheng Wang, Georgios Karakonstantis and Anupam Chattopadhyay

Session Title	SPECIAL DAY Hot Topic: Lightweight Security for Embedded Processors
Session Code / Room	10.1 / Saal 2
Date / Time	Thursday, 17 March 2016 / 11:00 – 12:30
Chair	Tilo Müller, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE
Co-Chair	Patrick Schaumont, Virginia Tech, US

10.1.1 11:00 – 11:30	Scaling Down: Lightweight Approaches to IoT Security Patrick Koeberl
10.1.2 11:30 – 12:00	SOFIA: Software and Control Flow Integrity Architecture Ruan de Clercq, Ronald De Keulenaer, Bart Coppens, Bohan Yang, Pieter Maene, Koen de Bosschere, Bart Preneel, Bjorn de Sutter and Ingrid Verbauwhede
10.1.3 12:00 – 12:30	Trust, But Verify: Why and How to Establish Trust in Embedded Devices Aurélien Francillon

Session Title	Does it Work or NoC?
Session Code / Room	10.2 / Konferenz 6
Date / Time	Thursday, 17 March 2016 / 11:00 – 12:30
Chair	Davide Bertozzi, University of Ferrara, IT
Co-Chair	Kees Goossens, Eindhoven University of Technology, NL

10.2.1 11:00 – 11:30	CrossOver: Clock Domain Crossing under Virtual-Channel Flow Control Michalis Paschou, Anastasios Psarras, Chrysostomos Nicopoulos and Giorgos Dimitrakopoulos
10.2.2 11:30 – 12:00	Correct Runtime Operation for NoCs through Adaptive-Region Protection Rawan Abdel-Khalek and Valeria Bertacco
10.2.3 12:00 – 12:30	Fault-Tolerant 3-D Network-on-Chip Design using Dynamic Link Sharing Seyyed Hossein Seyyedaghaei Rezaei, Mehdi Modarressi, Reza Yazdani Aminabadi and Masoud Daneshtalab

Session Title	Design Experiences for Multimedia and Communication Applications
Session Code / Room	10.3 / Konferenz 1
Date / Time	Thursday, 17 March 2016 / 11:00 – 12:30
Chair	Theocharis THEOCHARIDES, University of Cyprus, CY
Co-Chair	Steffen Paul, University Bremen, DE

10.3.1 11:00 – 11:30	Enabling the Heterogeneous Accelerator Model on Ultra-Low Power Microcontroller Platforms Francesco Conti, Daniele Palossi, Andrea Marongiu, Davide Rossi and Luca Benini
10.3.2 11:30 – 12:00	Thermal Optimization using Adaptive Approximate Computing for Video Coding Daniel Palomino, Muhammad Shafique, Altamiro Susin and Jörg Henkel
10.3.3 12:00 – 12:15	High Performance Time-of-Flight and Color Sensor Fusion with Image-Guided Depth Super Resolution Hannes Plank, Gerald Holweg, Thomas Herndl and Norbert Druml
10.3.4 12:15 – 12:30	Saturated Min-Sum Decoding: An “Afterburner” for LDPC Decoder Hardware S. Scholl, P. Schläfer and N. Wehn

Session Title	Stochastic Methods for Circuit Analysis & Synthesis
Session Code / Room	10.4 / Konferenz 2
Date / Time	Thursday, 17 March 2016 / 11:00 – 12:30
Chair	Michal Rewienski, Technical University of Gdansk, PL
Co-Chair	L. Miguel Silveira, INESC-ID, IST, U Lisboa, PT

10.4.1 11:00 – 11:30	Utilizing Macromodels in Floating Random Walk Based Capacitance Extraction Wenjian Yu, Bolong Zhang, Chao Zhang, Haiquan Wang and Luca Daniel
10.4.2 11:30 – 12:00	Variability and Statistical Analysis Flow for Dynamic Linear Systems with Large Number of Inputs A. Lucas Martins, Jorge Fernández Villena and L. Miguel Silveira
10.4.3 12:00 – 12:30	Variation-Aware Near Threshold Circuit Synthesis Mohammad Saber Golanbari, Saman Kiamehr, Mojtaba Ebrahimi and Mehdi B. Tahoori

Session Title	Enhancing Memory in Next-Generation Platforms
Session Code / Room	10.5 / Konferenz 3
Date / Time	Thursday, 17 March 2016 / 11:00 – 12:30
Chair	Fancisco Cazorla, Barcelona Supercomputing Center, ES
Co-Chair	Jeronimo Castrillon, Technische Universität Dresden, DE

10.5.1 11:00 – 11:30	Buffered Compares: Excavating the Hidden Parallelism Inside DRAM Architectures with Lightweight Logic Jinho Lee, Jung Ho Ahn and Kiyoung Choi
10.5.2 11:30 – 12:00	Large Vector Extensions Inside the HMC Marco A. Z. Alves, Matthias Diener, Paulo C. Santos and Luigi Carro
10.5.3 12:00 – 12:30	minFlash: A Minimalistic Clustered Flash Array Ming Liu, Sang-Woo Jun, Sungjin Lee, Jamey Hicks and Arvind

Session Title	Compilers and Tools for GPUs and MPSoCs
Session Code / Room	10.6 / Konferenz 4
Date / Time	Thursday, 17 March 2016 / 11:00 – 12:30
Chair	Frank Hannig, University of Erlangen-Nürnberg, DE
Co-Chair	Lars Bauer, Karlsruhe Institute of Technology, DE

10.6.1 11:00 – 11:30	An Optimized Task-Based Runtime System for Resource-Constrained Parallel Accelerators Daniele Cesarini, Andrea Marongiu and Luca Benini
10.6.2 11:30 – 12:00	A Fine-grained Performance Model for GPU Architectures Nicola Bombieri, Federico Busato and Franco Fummi
10.6.3 12:00 – 12:15	Critical Points Based Register-Concurrency Autotuning for GPUs Ang Li, Shuaiwen Leon Song, Akash Kumar, Eddy Z. Zhang, Daniel Chavarrìa-Miranda and Henk Corporaal
10.6.4 12:15 – 12:30	GRATER: An Approximation Workflow for Exploiting Data-Level Parallelism in FPGA Acceleration Atieh Lotfi, Abbas Rahimi, Amir Yazdanbakhsh, Hadi Esmaeilzadeh and Rajesh K. Gupta

Session Title	Reliable System Design
Session Code / Room	10.7 / Konferenz 5
Date / Time	Thursday, 17 March 2016 / 11:00 – 12:30
Chair	Mohamed Sabry Aly, Stanford University, US
Co-Chair	Semeen Rehman, Karlsruhe Institute of Technology, DE

10.7.1 11:00 – 11:30	A Holistic Tri-region MLC STT-RAM Design with Combined Performance, Energy, and Reliability Optimizations Wujie Wen, Mengjie Mao, Hai Li, Yiran Chen, Yukui Pei and Ning Ge
10.7.2 11:30 – 12:00	Thermal-aware TSV Repair for Electromigration in 3D ICs Shengcheng Wang, Mehdi B. Tahoori and Krishnendu Chakrabarty
10.7.3 12:00 – 12:30	Electrothermal Simulation of Bonding Wire Degradation under Uncertain Geometries Thorben Casper, Herbert De Gersem, Renaud Gillon, Tomas Gotthans, Tomas Kratochvil, Peter Meuris, Sebastian Schöps

Session Title	Lunch Time Keynote Session
Session Code / Room	11.0
Date / Time	Thursday, 17 March 2016 / 13:30 – 14:00
Chair	Luca Fanucci, University of Pisa, IT
Co-Chair	Matthias Schunter, Intel Corporation, DE

11.0.1
13:30 – 14:00

[Keynote] Secure Silicon: Enabler for the Internet of Things
Walden C. Rhines

Session Title	SPECIAL DAY Hot Topic: Embedded Security Applications
Session Code / Room	11.1 / Saal 2
Date / Time	Thursday, 17 March 2016 / 14:00 – 15:30
Chair	Tim Güneysu, University of Bremen, DE
Co-Chair	X. Sharon Hu, University of Notre Dame, US

11.1.1 14:00 – 14:30	Smart Grid Security Klaus Kursawe
11.1.2 14:30 – 15:00	Security In Industrie 4.0 — Challenges and Solutions for the Fourth Industrial Revolution Michael Waidner and Michael Kasper
11.1.3 15:00 – 15:30	Security for Automotive and the Internet of Things Paul Duplys, Hans Löhr, Herve Seudie and Robert Szerwinski

Session Title	Beating New Technology Paths for NoC
Session Code / Room	11.2 / Konferenz 6
Date / Time	Thursday, 17 March 2016 / 14:00 – 15:30
Chair	Partha Pande, WSU, US
Co-Chair	Sébastien Le Beux, Le Beux, FR

11.2.1 14:00 – 14:30	Cross-layer Floorplan Optimization For Silicon Photonic NoCs In Many-core Systems Ayse K. Coskun, Anjun Gu, Warren Jin, Ajay Joshi, Andrew B. Kahng, Jonathan Klamkin, Yenai Ma, John Recchio, Vaishnav Srinivas and Tiansheng Zhang
11.2.2 14:30 – 15:00	Adaptive Multi-Voltage Scaling in Wireless NoC for High Performance Low Power Applications Hemanta Kumar Mondal, Sri Harsha Gade, Raghav Kishore and Sujay Deb
11.2.3 15:00 – 15:30	Energy Efficient Transceiver in Wireless Network on Chip Architectures Vincenzo Catania, Andrea Mineo, Salvatore Monteleone, Maurizio Palesi and Davide Patti

Session Title	Microarchitectures and Workload Allocation for Energy Efficiency
Session Code / Room	11.3 / Konferenz 1
Date / Time	Thursday, 17 March 2016 / 14:00 – 15:30
Chair	Andrea Bartolini, Univ. of Bologna, IT
Co-Chair	Andreas Burg, EPFL, CH

11.3.1 14:00 – 14:30	Resistive Configurable Associative Memory for Approximate Computing Mohsen Imani, Abbas Rahimi and Tajana S. Rosing
11.3.2 14:30 – 15:00	Exploiting CPU-Load and Data Correlations in Multi-Objective VM Placement for Geo-Distributed Data Centers Ali Pahlevan, Pablo Garcia del Valle and David Atienza
11.3.3 15:00 – 15:15	Energy Efficiency in Cloud-Based MapReduce Applications through Better Performance Estimation Seyed Morteza Nabavinejad and Maziar Goudarzi
11.3.4 15:15 – 15:30	Unsupervised Power Modeling of Co-Allocated Workloads for Energy Efficiency in Data Centers Juan C. Salinas-Hilburg, Marina Zapater, José L. Risco-Martín, José M. Moya and José L. Ayala

Session Title	Automating Test Generation, Assertions and Diagnosis
Session Code / Room	11.4 / Konferenz 2
Date / Time	Thursday, 17 March 2016 / 14:00 – 15:30
Chair	Pablo Sanchez, University of Cantabria, ES
Co-Chair	Ronny Morad, IBM, IL

11.4.1 14:00 – 14:30	Automated Test Generation for Debugging Arithmetic Circuits Farimah Farahmandi and Prabhat Mishra
11.4.2 14:30 – 15:00	MCXplore: An Automated Framework for Validating Memory Controller Designs Mohamed Hassan and Hiren Patel
11.4.3 15:00 – 15:15	EAST: Efficient Assertion Simulation Techniques Debjyoti Bhattacharjee, Soumi Chattopadhyay and Ansuman Banerjee
11.4.4 15:15 – 15:30	Combinational Trace Signal Selection with Improved State Restoration for Post-Silicon Debug Siamack BeigMohammadi and Bijan Alizadeh

Session Title	Design of Efficient Microarchitectures
Session Code / Room	11.5 / Konferenz 3
Date / Time	Thursday, 17 March 2016 / 14:00 – 15:30
Chair	Dionisios Pnevmatikatos, Technical University of Crete, GR
Co-Chair	Todd Austin, University of Michigan, US

11.5.1 14:00 – 14:30	Practical Way Halting by Speculatively Accessing Halt Tags Daniel Moreau, Alen Bardizbanyan, Magnus Själander, David Whalley and Per Larsson-Edefors
11.5.2 14:30 – 15:00	Lazy Pipelines: Enhancing Quality in Approximate Computing G. Tziantzioulis, A. M. Gok, S. M. Faisal, N. Hardavellas, S. Ogrenci-Memik and S. Parthsarathy
11.5.3 15:00 – 15:30	High-Efficiency Logarithmic Number Unit Design based on an Improved Cotransformation Scheme Youri Popoff, Florian Scheidegger, Michael Schaffner, Michael Gautschi, Frank K. Gürkaynak and Luca Benini

Session Title	Applications of Reconfigurable Computing
Session Code / Room	11.6 / Konferenz 4
Date / Time	Thursday, 17 March 2016 / 14:00 – 15:30
Chair	Alessandro Cilardo, University of Naples Federico II, IT
Co-Chair	Koen Bertels, Delft University of Technology, NL

11.6.1 14:00 – 14:30	Efficient FPGA Acceleration of Convolutional Neural Networks Using Logical-3D Compute Array Atul Rahman, Jongeun Lee and Kiyoung Choi
11.6.2 14:30 – 15:00	Energy Efficient Video Fusion with Heterogeneous CPU-FPGA Devices Peng Sun, Alin Achim, Ian Hasler, Paul Hill and Jose Nunez-Yanez
11.6.3 15:00 – 15:30	Highly Efficient Reconfigurable Parallel Graph Cuts for Embedded Vision Antonis Nikitakis and Ioannis Papaefstathiou

Session Title	Naked Analog Synthesis
Session Code / Room	11.7 / Konferenz 5
Date / Time	Thursday, 17 March 2016 / 14:00 – 15:30
Chair	Árpád Árpád Bürmen, University of Ljubljana, SI
Co-Chair	Francisco Fernandez, IMSE-CNM, ES

11.7.1 14:00 – 14:30	Pareto Front Analog Layout Placement using Satisfiability Modulo Theories Sherif M. Saif, Mohamed Dessouky, M. Watheq El-Kharashi, Hazem Abbas and Salwa Nassar
11.7.2 14:30 – 15:00	Efficient Multiple Starting Point Optimization for Automated Analog Circuit Optimization via Recycling Simulation Data Bo Peng, Fan Yang, Changhao Yan, Xuan Zeng and Dian Zhou
11.7.3 15:00 – 15:30	PolyGP: Improving GP-Based Analog Optimization through Accurate High-Order Monomials and Semidefinite Relaxation Ye Wang, Constantine Caramanis and Michael Orshansky

Session Title	Interactive Presentations
Session Code / Room	IP5
Date / Time	Thursday, 17 March 2016 / 15:30 – 16:00

IP5-1	Reliability and Performance Trade-offs for 3D NoC-Enabled Multicore Chips Sourav Das, Janardhan Rao Doppa, Partha Pratim Pande and Krishnendu Chakrabarty
IP5-2	Memory-Access Aware DVFS for Network-on-Chip in CMPs Yuan Yao and Zhonghai Lu
IP5-3	A Dynamically Reconfigurable ECC Decoder Architecture Awais Sani, Philippe Coussy and Cyrille Chavet
IP5-4	Resistive Bloom Filters: From Approximate Membership to Approximate Computing with Bounded Errors Vahideh Akhlaghi, Abbas Rahimi and Rajesh K. Gupta
IP5-5	Real-Time System-Level Implementation of a Telepresence Robot Using an Embedded GPU Platform Muhammad Teguh Satria, Swathi Gurumani, Wang Zheng, Keng Peng Tee, Augustine Koh, Pan Yu, Kyle Rupnow and Deming Chen
IP5-6	Exploring Specialized Near-Memory Processing for Data Intensive Operations Salessawi Ferede Yitbarek, Tao Yang, Reetuparna Das and Todd Austin
IP5-7	Matlab to C Compilation Targeting Application Specific Instruction Set Processors Ioannis Latifis, Karthick Parashar, Grigoris Dimitroulakos, Hans Cappelle, Christakis Lezos, Konstantinos Masselos and Francky Catthoor
IP5-8	Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability Grace Li Zhang, Bing Li and Ulf Schlichtmann
IP5-9	PRADA: Combating Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms Prabal Basu, Rajesh Jayashankara Shridevi, Koushik Chakraborty and Sanghamitra Roy
IP5-10	A Power-Efficient 3-D On-Chip Interconnect for Multi-Core Accelerators with Stacked L2 Cache Kyungsu Kang, Sangho Park, Jong-Bae Lee, Luca Benini and Giovanni De Micheli
IP5-11	Power-Efficient Load-Balancing on Heterogeneous Computing Platforms Muhammad Usman Karim Khan, Muhammad Shafique, Apratim Gupta, Thomas Schumann and Jörg Henkel
IP5-12	Topaz: Mining High-Level Safety Properties from Logic Simulation Traces Ahmed Nassar, Fadi J. Kurdahi and Salam R. Zantout
IP5-13	Exploiting Transaction Level Models for Observability-aware Post-silicon Test Generation Farimah Farahmandi, Prabhat Mishra and Sandip Ray
IP5-14	SEERAD: A High Speed yet Energy-Efficient Rounding-based Approximate Divider Reza Zendegani, Mehdi Kamal, Arash Fayyazi, Ali Afzali-Kusha, Saeed Safari and Massoud Pedram
IP5-15	Improving Performance Guarantees in Wormhole Mesh NoC Designs Miloš Panić, Carles Hernandez, Jaume Abella, Antoni Roca, Eduardo Quiñonesy and Francisco J. Cazorla
IP5-16	A Data Layout Transformation (DLT) Accelerator: Architectural Support for Data Movement Optimization in Accelerated-centric Heterogeneous Systems Tung Thanh-Hoang, Amirali Shambayati and Andrew A. Chien
IP5-17	Ouessant: Flexible Integration of Dedicated Coprocessors in Systems On Chip Pierre-Henri Horrein, Philip-Dylan Gleonec, Erwan Libessart, André Lalevée and Matthieu Arzel
IP5-18	A novel Background Subtraction Scheme for in-Camera Acceleration in Thermal Imagery Antonis Nikitakis, Ioannis Papaefstathiou, Konstantinos Makantasis and Anastasios Doulamis
IP5-19	Radiation-Hardened DSP Configurations for Implementing Arithmetic Functions on FPGA Marcos Sanchez-Elez, Inmaculada Pardines, Felipe Serrano and Hortensia Mecha
IP5-20	Configuration Prefetching and Reuse for Preemptive Hardware Multitasking on Partially Reconfigurable FPGAs Aurelio Morales-Villanueva, Rohit Kumar and Ann Gordon-Ross
IP5-21	Analog Circuit Topological Feature Extraction with Unsupervised Learning of New Sub-Structures Hao Li, Fanshu Jiao and Alex Doboli
IP5-22	Design Automation Tasks Scheduling for Enhanced Parallel Execution of a State-of-the-Art Layout-Aware Sizing Approach David Neves, Ricardo Martins, Nuno Lourenço and Nuno Horta

Session Title	SPECIAL DAY Hot Topic: Design Methods for Security and Trust
Session Code / Room	12.1 / Saal 2
Date / Time	Thursday, 17 March 2016 / 16:00 – 17:30
Chair	Jean-Luc Danger, Télécom ParisTech, FR
Co-Chair	Ilia Polian, Universität Passau, DE

12.1.1 16:00 – 16:30	A Design Method for Remote Integrity Checking of Complex PCBs Aydin Aysu, Shravya Gaddam, Harsha Mandadi, Carol Pinto, Luke Wegryn and Patrick Schaumont
12.1.2 16:30 – 17:00	Quantifying Hardware Security Using Joint Information Flow Analysis Ryan Kastner, Wei Hu and Alric Althoff
12.1.3 17:00 – 17:30	Instruction Set Extensions for Secure Applications Francesco Regazzoni and Paolo Ienne

Session Title	Hot Topic: Exploiting New Transistor Technologies to Enhance Hardware Security (without PUFs!)
Session Code / Room	12.2 / Konferenz 6
Date / Time	Thursday, 17 March 2016 / 16:00 – 17:30
Organisers	Michael Niemier, University of Notre Dame, South Bend, US
Chair	Sri Parameswaran, The University of New South Wales, AU

12.2.1 16:00 – 16:30	Hardware Security Through Chain Assurance Yaw Obeng, Colm Nolan and David Brown
12.2.2 16:30 – 17:00	Leverage Emerging Technologies For DPA-Resilient Block Cipher Design Yu Bi, Kaveh Shamsi, Jiann-Shiun Yuan, Francois-Xavier Standaer and Yier Jin
12.2.3 17:00 – 17:30	Using Emerging Technologies for Hardware Security Beyond PUFs An Chen, X. Sharon Hu, Yier Jin, Michael Niemier and Xunzhao Yin

Session Title	System Support for Resilience and Robustness
Session Code / Room	12.3 / Konferenz 1
Date / Time	Thursday, 17 March 2016 / 16:00 – 17:30
Chair	Oliver Bringmann, University of Tuebingen, DE
Co-Chair	Dirk Stroobandt, Ghent University, BE

12.3.1 16:00 – 16:30	Effect of LFSR Seeding, Scrambling and Feedback Polynomial on Stochastic Computing Accuracy Jason H. Anderson, Yuko Hara-Azumi and Shigeru Yamashita
12.3.2 16:30 – 17:00	Efficient Program Tracing and Monitoring Through Power Consumption — With a Little Help from the Compiler Carlos Moreno, Sean Kauffman and Sebastian Fischmeister
12.3.3 17:00 – 17:15	FLIC: Fast, Lightweight Checkpointing for Mobile Virtualization using NVRAM Kan Zhong, Duo Liu, Liang Liang, Linbo Long, Yi Lin and Zili Shao
12.3.4 17:15 – 17:30	PAIS: Parallelization Aware Instruction Scheduling for Improving Soft-error Reliability of GPU-based Systems Haeseung Lee, Hsinchung Chen and Mohammad Abdullah Al Faruque

Session Title	Simulating Everything: From Timing to Instructions
Session Code / Room	12.4 / Konferenz 2
Date / Time	Thursday, 17 March 2016 / 16:00 – 17:30
Chair	Elena Ioana Vatajelu, Politecnico di Torino, IT
Co-Chair	Valeria Bertacco, University of Michigan, US

12.4.1 16:00 – 16:30	Accelerating Source-Level Timing Simulation Simon Schulz and Oliver Bringmann
12.4.2 16:30 – 17:00	Sparsity-Oriented Sparse Solver Design for Circuit Simulation Xiaoming Chen, Lixue Xia, Yu Wang and Huazhong Yang
12.4.3 17:00 – 17:15	Integration of Mixed-signal Components into Virtual Platforms for Holistic Simulation of Smart Systems Enrico Fraccaroli, Michele Lora, Sara Vinco, Davide Quaglia and Franco Fummi
12.4.4 17:15 – 17:30	Decision Tree Generation for Decoding Irregular Instructions Katsumi Okuda and Haruhiko Takeyama

Session Title	Accelerator Design and Heterogeneous Architectures
Session Code / Room	12.5 / Konferenz 3
Date / Time	Thursday, 17 March 2016 / 16:00 – 17:30
Chair	Cristina Silvano, Politecnico di Milano, IT
Co-Chair	Todd Austin, University of Michigan, US

12.5.1 16:00 – 16:30	A Reconfigurable Heterogeneous Multicore with a Homogeneous ISA Jeckson Dellagostin Souza, Luigi Carro, Mateus Beck Rutzig and Antonio Carlos Schneider Beck
12.5.2 16:30 – 17:00	The Neuro Vector Engine: Flexibility to Improve Convolutional Net Efficiency for Wearable Vision Maurice Peemen, Runbin Shi, Sohan Lal, Ben Juurlink, Bart Mesman and Henk Corporaal
12.5.3 17:00 – 17:15	Improving Scalability of CMPs with Dense ACCs Coverage Nasibeh Teimouri, Hamed Tabkhi and Gunar Schirner
12.5.4 17:15 – 17:30	Hardware Accelerator for Analytics of Sparse Data Eriko Nurvitadhi, Asit Mishra, Yu Wang, Ganesh Venkatesh and Debbie Marr

Session Title	Reconfigurable Computing Platforms and Architectures
Session Code / Room	12.6 / Konferenz 4
Date / Time	Thursday, 17 March 2016 / 16:00 – 17:30
Chair	Dirk Stroobandt, Ghent University, BE
Co-Chair	Jürgen Becker, Karlsruhe Institute of Technology, DE

12.6.1 16:00 – 16:30	Securing the Cloud with Reconfigurable Computing: An FPGA Accelerator for Homomorphic Encryption Alessandro Cilardo and Domenico Argenziano
12.6.2 16:30 – 17:00	Throughput Oriented FPGA Overlays Using DSP Blocks Abhishek Kumar Jain, Douglas L. Maskell and Suhaib A. Fahmy
12.6.3 17:00 – 17:30	Run-time Phase Prediction for a Reconfigurable VLIW Processor Qi Guo, Anderson Sartor, Anthony Brandon, Antonio C. S. Beck, Xuehai Zhou and Stephan Wong

Session Title	Formal System Level Verification
Session Code / Room	12.7 / Konferenz 5
Date / Time	Thursday, 17 March 2016 / 16:00 – 17:30
Chair	Mathias Soeken, EPFL, CH
Co-Chair	Gianpiero Cabodi, Politecnio di Torino, IT

12.7.1 16:00 – 16:30	ADVOCAT: Automated Deadlock Verification for On-chip Cache Coherence and Interconnects Freek Verbeek, Pooria M. Yaghini, Ashkan Eghbal and Nader Bagherzadeh
12.7.2 16:30 – 17:00	Guarantees for Runnable Entities with Heterogeneous Real-Time Requirements Leonie Ahrendts, Zain A. H. Hammadeh and Rolf Ernst
12.7.3 17:00 – 17:30	Validating Scheduling Transformation for Behavioral Synthesis Zhenkun Yang, Kecheng Hao, Kai Cong, Li Lei, Sandip Ray and Fei Xie