^{1}, Yuko Hara-Azumi

^{2}and Shigeru Yamashita

^{3}

^{1}Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada.

^{2}Department of Communications and Computer Engineering, Tokyo Institute of Technology, Tokyo, Japan.

^{3}Department of Computer Science, Ritsumeikan University, Shiga, Japan

Stochastic computing (SC) [1] has received attention recently as a paradigm to improve energy efficiency and fault tolerance. SC uses hardware-generated random bitstreams to represent numbers in the [0:1] range — the number represented is the probability of a bit in the stream being logic-1. The generation of random bitstreams is typically done using linear-feedback shift register (LFSR)-based random number generators. In this paper, we consider how best to design such LFSR-based stochastic bitstream generators, as a means of improving the accuracy of stochastic computing. Three design criteria are evaluated: 1) LFSR seed selection, 2) the utility of scrambling LFSR output bits, and 3) the LFSR polynomials (i.e. locations of the feedback taps) and whether they should be unique vs. uniform across stream generators. For a recently proposed multiplexer-based stochastic logic architecture [8], we demonstrate that careful seed selection can improve accuracy results vs. the use of arbitrarily selected seeds. For example, we show that stochastic logic with seed-optimized 255-bit stream lengths achieves accuracy better than that of using 1023-bit stream lengths with arbitrary seeds: an improvement of over 4× in energy for equivalent accuracy.