SystemC Transaction-level modeling (TLM) provides high-level component-based models for SoCs, for which assertion-Based-Verification (ABV) allows property checking early in the design cycle. We introduce the notion of

This new notion can already be expressed in languages like PSL, for which there exist tools to generate ABV monitors. But the definition of dedicated patterns makes it easier to write the properties. Moreover we define a direct translation of these patterns into SystemC monitors, and we show that it avoids the combinatorial explosion that would occur during a prior translation into PSL.