9.6 Reliability and Optimization Techniques for Analog Circuits

Time	Label	Presentation Title Authors
08:30	9.6.1	SLOT: A SUPERVISED LEARNING MODEL TO PREDICT DYNAMIC TIMING ERRORS OF FUNCTIONAL UNITS Speaker: Xun Jiao, University of California San Diego, US Authors: Xun Jiao¹, Yu Jiang², Abbas Rahimi³ and Rajesh Gupta¹ ¹University of California, San Diego, US; ²Tsinghua University, CN; ³University of California, Berkeley, US Abstract Dynamic timing errors (DTEs), that are caused by the timing violations of sensitized critical timing paths, have emerged as an important threat to the reliability of digital circuits. Existing approaches model the DTEs without considering the impact of input operands on dynamic path sensitization, resulting in loss of accuracy. The diversity of input operands leads to complex path sensitization behaviors, making it hard to represent in DTE modeling. In this paper, we propose SLoT, a supervised learning model to predict the output of functional units (FUs) to be one of two timing classes: {timing correct, timing erroneous}, as a function of input operands and clock period. We apply random forest classification (RFC) method to construct SLoT, by using input operands, computation history and circuit toggling as input features and outputs' timing classes as labels. The outputs timing classes are measured using gate-level simulation (GLS) of a post place-and-route design in TSMC 45nm process. For evaluation, we apply SLoT to several FUs and on average 95% predictions are consistent with GLS, which is 6.3X higher compared to the existing instruction-level model. SLoT-based reliability analysis of FUs under different benchmark datasets can achieve 0.7-4.8% average difference compared with GLS-based analysis, and execute more than 20X faster than GLS. Download Paper (PDF; Only available from the DATE venue WiFi)
09:00	9.6.2	EXPLOITING DATA-DEPENDENCE AND FLIP-FLOP ASYMMETRY FOR ZERO-OVERHEAD SYSTEM SOFT ERROR MITIGATION Speaker: Liangzhen Lai, ARM Inc., US Authors: Liangzhen Lai and Vikas Chandra, ARM, US Abstract Soft error is one of the major threats for resilient computing. Unlike SRAM soft error, which can be effectively protected by ECC, Flip-Flop soft error protection can be costly. We observe that flip-flops/latches can have asymmetric soft error rates when storing different logic values. This asymmetry can be used in conjunction with the different signal probabilities of registers in a design. In this work, we first demonstrate that flip-flop cells can be designed to have different soft error rates when storing different logic values. We also propose a methodology to match registers in a design with the flip-flop cells that minimize the soft error rates. Experimental results on commercial processor show that, with only flip-flop layout changes, our proposed scheme can reduce system SER by 16% with no overhead in performance, power and area. The system SER reduction can be improved to 48% with schematic changes and 6.7% average increase in flip-flop area. Download Paper (PDF; Only available from the DATE venue WiFi)
09:15	9.6.3	SUBGRADIENT BASED MULTIPLE-STARTING-POINT ALGORITHM FOR NON-SMOOTH OPTIMIZATION OF ANALOG CIRCUITS Speaker: Wenlong Lv, Fudan University, CN Authors: Wenlong Lv¹, Fan Yang¹, Changhao Yan¹, Dian Zhou² and Xuan Zeng¹ ¹Fudan University, CN; ²University of Texas at Dallas, US Abstract Starting from a set of starting points, the multiple-starting-point optimization searches the local optimums by gradient-guided local search. The global optimum is selected from these local optimums. The region-hit property of the multiple-starting-point optimization makes the multiple-starting-point approach more likely to reach the global optimum. However, for non-smooth objective functions, e.g., worst-case optimization, the traditional gradient based local search methods may stuck at non-smooth points, even if the objective function is smooth ``almost everywhere''. In this paper, we propose a subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. Subgradients instead of traditional gradients are used to guide the local search of the non-smooth optimization. The Shor's R algorithm is used to accelerate the subgradient based local search. A two-stage optimization strategy is proposed to deal with the constraints in analog circuit optimization. Our experiments on 2 circuits show that the proposed method is very efficient for worst-case optimization. The proposed approach can achieve much better solutions with less simulations, compared with the traditional gradient based method, smoothing approximation method, smooth relaxation method and differential evolution algorithms. Download Paper (PDF; Only available from the DATE venue WiFi)
09:30	9.6.4	EFFICIENT YIELD OPTIMIZATION METHOD USING A VARIABLE K-MEANS ALGORITHM FOR ANALOG IC SIZING Speaker: António Canelas, Instituto de Telecomunicações/Instituto Superior Técnico – ULisbon, PT Authors: António Canelas¹, Ricardo Martins¹, Ricardo Povoa², Nuno Lourenço¹ and Nuno Horta¹ ¹Instituto de Telecomunicações/Instituto Superior Técnico – ULisbon, PT; ²Instituto de Telecomunicações/Instituto Superior Técnico - ULisbon, PT Abstract This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00	IP4-13, 140	ENHANCING ANALOG YIELD OPTIMIZATION FOR VARIATION-AWARE CIRCUITS SIZING Speaker: Ons Lahiouel, Concordia University, CA Authors: Ons Lahiouel, Mohamed H. Zaki and Sofiene Tahar, Concordia University, CA Abstract This paper presents a novel approach for improving automated analog yield optimization using a two step exploration strategy. First, a global optimization phase relies on a modiﬁed Lipschitizian optimization to sample the potential optimal sub-regions of the feasible design space. The search locates a design point near the optimal solution that is used as a starting point by a local optimization phase. The local search constructs linear interpolating surrogate models of the yield to explore the basin of convergence and to rapidly reach the global optimum. Experimental results show that our approach locates higher quality design points in terms of yield rate within less run time and without affecting the accuracy. Download Paper (PDF; Only available from the DATE venue WiFi)
10:01	IP4-14, 276	A NEW SAMPLING TECHNIQUE FOR MONTE CARLO-BASED STATISTICAL CIRCUIT ANALYSIS Speaker: Hiwa Mahmoudi, Vienna University of Technology, AT Authors: Hiwa Mahmoudi and Horst Zimmermann, Vienna University of Technology, AT Abstract Variability is a fundamental issue which gets exponentially worse as CMOS technology shrinks. Therefore, characterization of statistical variations has become an important part of the design phase. Monte Carlo-based simulation method is a standard technique for statistical analysis and modeling of integrated circuits. However, crude Monte Carlo sampling based on pseudorandom selection of parameter variations suffers from low convergence rates and thus, providing high accuracy is computationally expensive. In this work, we present an extensive study on the performance of two widely used techniques, Latin Hypercube and Low Discrepancy sampling methods, and compare their speed-up and accuracy performance properties. It is shown that these methods can exhibit a better efficiency as compared to the pseudorandom sampling but only in limited applications. Therefore, we propose a new sampling scheme that exploits the benefits of both methods by combining them. Through representative circuit examples, it is shown that the proposed sampling technique provides a major improvement in terms of computational effort and offers better properties as compared to each solely. Download Paper (PDF; Only available from the DATE venue WiFi)
10:02	IP4-15, 257	AUTOMATIC TECHNOLOGY MIGRATION OF ANALOG IC DESIGNS USING GENERIC CELL LIBRARIES Speaker: Nuno Horta, Instituto de Telecomunicações / Instituto Superior Técnico, PT Authors: Jose Cachaco¹, Nuno Machado¹, Nuno Lourenco¹, Jorge Guilherme² and Nuno Horta³ ¹Instituto de Telecomunicacoes/Instituto Superior Tecnico, PT; ²Instituto de Telecomunicacoes/Instituto Politecnico de Tomar, PT; ³Instituto de Telecomunicações/Instituto Superior Técnico, PT Abstract This paper addresses the problem of automatic technology migration of analog IC designs. The proposed approach introduces a new level of abstraction, for EDA tools addressing analog IC design, allowing a systematic and effortless adaption of a design to a new technology. The new abstraction level is based on generic cell libraries, which includes topology and testbenches descriptions for specific circuit classes. The new approach is implemented and tested using a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, and is validated for the sizing and optimization of continuous-time comparators, including technology migration between two different design nodes, respectively, XFAB 350 nm technology (XH035) and ATMEL 150 nm SOI technology (AT77K). Download Paper (PDF; Only available from the DATE venue WiFi)
10:03	IP4-16, 440	NOISE-SENSITIVE FEEDBACK LOOP IDENTIFICATION IN LINEAR TIME-VARYING ANALOG CIRCUITS Speaker: Peng Li, Texas A&M University, US Authors: Ang Li¹, Peng Li¹, Tingwen Huang² and Edgar Sánchez-Sinencio¹ ¹Texas A&M University, US; ²Texas A&M University at Qatar, QA Abstract The continuing scaling of VLSI technology and design complexity has rendered robustness of analog circuits a significant concern. Parasitic effects may introduce unexpected marginal instability within multiple noise-sensitive loops and hence jeopardize circuit operation and processing precision. The Loop Finder algorithm has been recently proposed to allow detection of noise-sensitive return loops for circuits that are described using a linear time-invariant (LTI) system model. However, many practical circuits such as switched-capacitor filters and mixers present time-varying behaviors which are intrinsically coupled with noise propagation and introduce new noise generation mechanisms. For the first time, we take an in-depth look into the marginal instability of linear periodically time-varying (LPTV) analog circuits and further develop an algorithm for efficient identification of noise-sensitive loops, unifying the solution to noise sensitivity analysis for both LTI and LPTV circuits. Download Paper (PDF; Only available from the DATE venue WiFi)
10:00		End of session Coffee Break in Exhibition Area On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Tuesday, March 28, 2017 Coffee Break 10:30 - 11:30 Coffee Break 16:00 - 17:00 Wednesday, March 29, 2017 Coffee Break 10:00 - 11:00 Coffee Break 16:00 - 17:00 Thursday, March 30, 2017 Coffee Break 10:00 - 11:00 Coffee Break 15:30 - 16:00

Time

Label

Presentation Title
Authors

08:30

9.6.1

SLOT: A SUPERVISED LEARNING MODEL TO PREDICT DYNAMIC TIMING ERRORS OF FUNCTIONAL UNITS
Speaker:
Xun Jiao, University of California San Diego, US
Authors:
Xun Jiao¹, Yu Jiang², Abbas Rahimi³ and Rajesh Gupta¹
¹University of California, San Diego, US; ²Tsinghua University, CN; ³University of California, Berkeley, US
Abstract
Dynamic timing errors (DTEs), that are caused by the timing violations of sensitized critical timing paths, have emerged as an important threat to the reliability of digital circuits. Existing approaches model the DTEs without considering the impact of input operands on dynamic path sensitization, resulting in loss of accuracy. The diversity of input operands leads to complex path sensitization behaviors, making it hard to represent in DTE modeling. In this paper, we propose SLoT, a supervised learning model to predict the output of functional units (FUs) to be one of two timing classes: {timing correct, timing erroneous}, as a function of input operands and clock period. We apply random forest classification (RFC) method to construct SLoT, by using input operands, computation history and circuit toggling as input features and outputs' timing classes as labels. The outputs timing classes are measured using gate-level simulation (GLS) of a post place-and-route design in TSMC 45nm process. For evaluation, we apply SLoT to several FUs and on average 95% predictions are consistent with GLS, which is 6.3X higher compared to the existing instruction-level model. SLoT-based reliability analysis of FUs under different benchmark datasets can achieve 0.7-4.8% average difference compared with GLS-based analysis, and execute more than 20X faster than GLS.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:00

9.6.2

EXPLOITING DATA-DEPENDENCE AND FLIP-FLOP ASYMMETRY FOR ZERO-OVERHEAD SYSTEM SOFT ERROR MITIGATION
Speaker:
Liangzhen Lai, ARM Inc., US
Authors:
Liangzhen Lai and Vikas Chandra, ARM, US
Abstract
Soft error is one of the major threats for resilient computing. Unlike SRAM soft error, which can be effectively protected by ECC, Flip-Flop soft error protection can be costly. We observe that flip-flops/latches can have asymmetric soft error rates when storing different logic values. This asymmetry can be used in conjunction with the different signal probabilities of registers in a design. In this work, we first demonstrate that flip-flop cells can be designed to have different soft error rates when storing different logic values. We also propose a methodology to match registers in a design with the flip-flop cells that minimize the soft error rates. Experimental results on commercial processor show that, with only flip-flop layout changes, our proposed scheme can reduce system SER by 16% with no overhead in performance, power and area. The system SER reduction can be improved to 48% with schematic changes and 6.7% average increase in flip-flop area.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:15

9.6.3

SUBGRADIENT BASED MULTIPLE-STARTING-POINT ALGORITHM FOR NON-SMOOTH OPTIMIZATION OF ANALOG CIRCUITS
Speaker:
Wenlong Lv, Fudan University, CN
Authors:
Wenlong Lv¹, Fan Yang¹, Changhao Yan¹, Dian Zhou² and Xuan Zeng¹
¹Fudan University, CN; ²University of Texas at Dallas, US
Abstract
Starting from a set of starting points, the multiple-starting-point optimization searches the local optimums by gradient-guided local search. The global optimum is selected from these local optimums. The region-hit property of the multiple-starting-point optimization makes the multiple-starting-point approach more likely to reach the global optimum. However, for non-smooth objective functions, e.g., worst-case optimization, the traditional gradient based local search methods may stuck at non-smooth points, even if the objective function is smooth ``almost everywhere''. In this paper, we propose a subgradient based multiple-starting-point algorithm for non-smooth optimization of analog circuits. Subgradients instead of traditional gradients are used to guide the local search of the non-smooth optimization. The Shor's R algorithm is used to accelerate the subgradient based local search. A two-stage optimization strategy is proposed to deal with the constraints in analog circuit optimization. Our experiments on 2 circuits show that the proposed method is very efficient for worst-case optimization. The proposed approach can achieve much better solutions with less simulations, compared with the traditional gradient based method, smoothing approximation method, smooth relaxation method and differential evolution algorithms.
Download Paper (PDF; Only available from the DATE venue WiFi)

09:30

9.6.4

EFFICIENT YIELD OPTIMIZATION METHOD USING A VARIABLE K-MEANS ALGORITHM FOR ANALOG IC SIZING
Speaker:
António Canelas, Instituto de Telecomunicações/Instituto Superior Técnico – ULisbon, PT
Authors:
António Canelas¹, Ricardo Martins¹, Ricardo Povoa², Nuno Lourenço¹ and Nuno Horta¹
¹Instituto de Telecomunicações/Instituto Superior Técnico – ULisbon, PT; ²Instituto de Telecomunicações/Instituto Superior Técnico - ULisbon, PT
Abstract
This paper presents the study and implementation of a new efficient yield optimization technique for multi-objective optimization-based automatic analog integrated circuit sizing. The approach uses a commercial electrical simulator and standard process design kit (PDK) models to perform, during the optimization process, the same Monte Carlo (MC) simulations that designers use. The proposed yield estimation technique reduces the number of required MC simulations by using the k-means algorithm, with a variable number of clusters, to select only a handful potential solutions where the MC simulations are performed. Due to the use of a commercial simulator tool and foundry supplied PDK models the developed methodology provides the most accurate and reliable results, and also, the variable k-means algorithm is able to achieve 91% reduction in the total number of the MC simulations required for an optimization, when considering MC simulations for all solutions. Moreover, this new approach presents a 50% increase in speed performance when comparing to a previous yield optimization technique also using k-means and MC simulations.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

IP4-13, 140

ENHANCING ANALOG YIELD OPTIMIZATION FOR VARIATION-AWARE CIRCUITS SIZING
Speaker:
Ons Lahiouel, Concordia University, CA
Authors:
Ons Lahiouel, Mohamed H. Zaki and Sofiene Tahar, Concordia University, CA
Abstract
This paper presents a novel approach for improving automated analog yield optimization using a two step exploration strategy. First, a global optimization phase relies on a modiﬁed Lipschitizian optimization to sample the potential optimal sub-regions of the feasible design space. The search locates a design point near the optimal solution that is used as a starting point by a local optimization phase. The local search constructs linear interpolating surrogate models of the yield to explore the basin of convergence and to rapidly reach the global optimum. Experimental results show that our approach locates higher quality design points in terms of yield rate within less run time and without affecting the accuracy.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:01

IP4-14, 276

A NEW SAMPLING TECHNIQUE FOR MONTE CARLO-BASED STATISTICAL CIRCUIT ANALYSIS
Speaker:
Hiwa Mahmoudi, Vienna University of Technology, AT
Authors:
Hiwa Mahmoudi and Horst Zimmermann, Vienna University of Technology, AT
Abstract
Variability is a fundamental issue which gets exponentially worse as CMOS technology shrinks. Therefore, characterization of statistical variations has become an important part of the design phase. Monte Carlo-based simulation method is a standard technique for statistical analysis and modeling of integrated circuits. However, crude Monte Carlo sampling based on pseudorandom selection of parameter variations suffers from low convergence rates and thus, providing high accuracy is computationally expensive. In this work, we present an extensive study on the performance of two widely used techniques, Latin Hypercube and Low Discrepancy sampling methods, and compare their speed-up and accuracy performance properties. It is shown that these methods can exhibit a better efficiency as compared to the pseudorandom sampling but only in limited applications. Therefore, we propose a new sampling scheme that exploits the benefits of both methods by combining them. Through representative circuit examples, it is shown that the proposed sampling technique provides a major improvement in terms of computational effort and offers better properties as compared to each solely.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:02

IP4-15, 257

AUTOMATIC TECHNOLOGY MIGRATION OF ANALOG IC DESIGNS USING GENERIC CELL LIBRARIES
Speaker:
Nuno Horta, Instituto de Telecomunicações / Instituto Superior Técnico, PT
Authors:
Jose Cachaco¹, Nuno Machado¹, Nuno Lourenco¹, Jorge Guilherme² and Nuno Horta³
¹Instituto de Telecomunicacoes/Instituto Superior Tecnico, PT; ²Instituto de Telecomunicacoes/Instituto Politecnico de Tomar, PT; ³Instituto de Telecomunicações/Instituto Superior Técnico, PT
Abstract
This paper addresses the problem of automatic technology migration of analog IC designs. The proposed approach introduces a new level of abstraction, for EDA tools addressing analog IC design, allowing a systematic and effortless adaption of a design to a new technology. The new abstraction level is based on generic cell libraries, which includes topology and testbenches descriptions for specific circuit classes. The new approach is implemented and tested using a state-of-the-art multi-objective multi-constraint circuit-level optimization tool, and is validated for the sizing and optimization of continuous-time comparators, including technology migration between two different design nodes, respectively, XFAB 350 nm technology (XH035) and ATMEL 150 nm SOI technology (AT77K).
Download Paper (PDF; Only available from the DATE venue WiFi)

10:03

IP4-16, 440

NOISE-SENSITIVE FEEDBACK LOOP IDENTIFICATION IN LINEAR TIME-VARYING ANALOG CIRCUITS
Speaker:
Peng Li, Texas A&M University, US
Authors:
Ang Li¹, Peng Li¹, Tingwen Huang² and Edgar Sánchez-Sinencio¹
¹Texas A&M University, US; ²Texas A&M University at Qatar, QA
Abstract
The continuing scaling of VLSI technology and design complexity has rendered robustness of analog circuits a significant concern. Parasitic effects may introduce unexpected marginal instability within multiple noise-sensitive loops and hence jeopardize circuit operation and processing precision. The Loop Finder algorithm has been recently proposed to allow detection of noise-sensitive return loops for circuits that are described using a linear time-invariant (LTI) system model. However, many practical circuits such as switched-capacitor filters and mixers present time-varying behaviors which are intrinsically coupled with noise propagation and introduce new noise generation mechanisms. For the first time, we take an in-depth look into the marginal instability of linear periodically time-varying (LPTV) analog circuits and further develop an algorithm for efficient identification of noise-sensitive loops, unifying the solution to noise sensitivity analysis for both LTI and LPTV circuits.
Download Paper (PDF; Only available from the DATE venue WiFi)

10:00

End of session
Coffee Break in Exhibition Area

On all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area.

Tuesday, March 28, 2017