Chair: Ingo Sander, Royal Institute of Technology, SE, Contact

Co-Chair: Andreas Gerstlauer, University of Texas at Austin, US, Contact

Topic Members (click to open)

Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

Chair: Andreas Herkersdorf, Technische Universität München, DE, Contact

Co-Chair: Nikil Dutt, University of California, Irvine, US, Contact

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High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for hardware/software co-design and partitioning; control and data flow analysis; hardware/software interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation and binding techniques; multi-objective optimization techniques (performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; hw/sw design patterns for multi-core system on chip (MPSoC) and distributed, networked embedded systems; system-level design of heterogeneous computing systems.

Chair: Elena Ioana Vatajelu, TIMA Laboratory, FR, Contact

Co-Chair: Valeria Bertacco, University of Michigan, US, Contact

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Simulation-based validation and verification; acceleration-driven and emulation-based validation; post-silicon verification; online checkers and runtime verification targeting new and traditional architectures and addressing the verification challenge at any level, from system to circuit level; diagnosing and debugging solutions for any of the verification platforms above; testbenches, checkers, assertions and monitor generation for verification; multi-domain simulation techniques; validation of cyber-physical systems, SoCs and emerging architectures.

Chair: Christoph Scholl, University Freiburg, DE, Contact

Co-Chair: Armin Biere, Universitaet Linz, AT, Contact

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Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction and decomposition techniques); technologies supporting formal verification; semi-formal verification techniques; formal verification of IPs, SoCs, and cores; integration of verification into design flows; challenges of multi-cores, both as verification targets and as verification host platforms.

Chair: André Ivanov, , CA, Contact

Co-Chair: Georges Gielen, Katholieke Universiteit Leuven, BE, Contact

Topic Members (click to open)

Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.

Chair: Alberto Macii, Politecnico di Torino, IT, Contact

Co-Chair: Naehyuck Chang, Korea Advanced Institute of Science and Technology (KAIST), KR, Contact

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Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Energy harvesting and battery modeling and design.

Chair: Luca Carloni, Columbia University, US, Contact

Co-Chair: Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact

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Architecture and modeling techniques for NoC; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security and power management; Techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; Integration of external interfaces/memory controllers with NoCs; Cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; Programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

Chair: Cristina Silvano, Politecnico di Milano, IT, Contact

Co-Chair: Elaheh Bozorgzadeh, University of California, Irvine, US, Contact

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Architectural and micro-architectural design techniques; memory systems; power and energy efficient architectures; multi/many-core architectures; multi-threading techniques and support for parallelism; application-specific processors and accelerators; architectural support for reliability, security, timing predictability.

Chair: Giovanni Ansaloni, University of Lugano, CH, Contact

Co-Chair: Jose L. Ayala, Complutense University of Madrid, ES, Contact

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Methods, techniques and architectures for counteracting variability of digital circuits and systems due to manufacturing, thermal or aging effects; design and run-time thermal, variability and reliability management of SoCs and multi-core platforms (both at hardware and software level); modeling and optimization approaches for manufacturing and temperature variations and degradation mechanisms in emerging 3D integration and manufacturing technologies.

Topic Members (click to open)

Reconfigurable computing platforms and architectures; heterogeneous platforms (FPGA/GPU/CPU); reconfigurable processors; reconfigurable computing for high performance and data centers; statically and dynamically reconfigurable and reprogrammable systems and components; FPGA architectures and FPGA circuit design; design methods and tools for reconfigurable computing and communication systems.

Chair: L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact

Co-Chair: Tiziano Villa, University of Verona, IT, Contact

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Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments. Parasitic and variation-aware extraction for on-chip interconnect and passives; Macro-modeling, behavioral and reduced order modeling; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate.

Chair: Aida Todri, CNRS, Fr, Contact

Co-Chair: Subhasish Mitra, Stanford University, US, Contact

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Modeling, circuit design and design automation flows for future computing including: non-CMOS logic based on emerging devices (e.g., carbon nanotube or graphene based FETs, TFETs, NWFETs, single electron transistors, NEMS etc.); alternative interconnect technologies (e.g., optical, RF, 3D, carbon nanotubes, graphene nanoribbons, spintronics, etc.); monolithic 3D integration (TSV modeling and design space exploration).

Chair: Jean-Michel Portal, IM2NP, FR, Contact

Co-Chair: Pierre-Emmanuel Gaillardon, University of Utah, US, Contact

Topic Members (click to open)

Modeling, circuit design and design automation flows for future data storage including: non-CMOS memory (e.g., MRAM, STT-RAM, FeRAM, PCRAM, RRAM, OxRAM, quantum dots etc.); advances in flash memory technology; memory-centric architectures (e.g., logic-in-memory, associative memories, non-volatile cache etc.); memory management techniques for emerging memories.

Chair: Andreas Burg, EPFL, CH, Contact

Co-Chair: Muhammad Shafique, Technische Universität Wien, AT, Contact

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Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, high performance computing clusters, data centers, cloud systems and cyber-physical systems. Topics of interest include, but are not limited to: software architectures for energy-efficient computing, virtualization, energy-efficient memory, processor, or communication architectures including non-volatile memory architectures and their use as storage components in datacenters, heterogeneous computing, resource management techniques including adaptive/learning-based methods, innovative data-center management strategies, big-data management, data centers powered by renewable energy sources, and data centers in smart-grids.

Chair: Steffen Paul, Universität Bremen, DE, Contact

Co-Chair: Theo Theocharides, University of Cyprus, CY, Contact

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Application design experiences for communication, multimedia and consumer systems such as smartphones, smart-books/tablets including digital integrated circuit design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software-defined/cognitive radio systems; embedded systems design in the field of audio, video and computer vision domains; Application Specific Processors (ASP), Digital Signal Processors (DSP), Multi-Processor Systems on Chip (MPSoC) and Network on Chip (NoC) designs for these domains.

Chair: David Boyle, Imperial College London, GB, Contact

Co-Chair: Davide Brunelli, DISI - University of Trento, IT, Contact

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Design experiences for automotive systems, smart energy systems, energy scavenging and harvesting for embedded systems, and related applications. This includes analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures, integrated sensors and transducers, RF architectures, in-vehicle networks, systems for electric vehicles, networks of systems (including car-to-car and car-to-infrastructure networks), and innovative concepts for power distribution, energy storage, and grid monitoring. Finally, topics of interest are also hardware solutions for run-time system management, including self-diagnostics and repair, energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems, and optimization of system energy efficiency.

Chair: Francisco Rincon, EPFL, CH, Contact

Co-Chair: Olivier Romain, ENSEA, FR, Contact

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Design experiences covering the use of IoT, wireless body sensor networks, assistive and wearable technologies for healthcare, rehabilitation and wellness. This includes but is not limited to: technologies for ultra-low/zero power systems for personal vital sign monitoring (such as heart rate, fitness devices); body area networks; mobile systems for motor disorder assessment and rehabilitation; wearable computing technologies, devices and systems for personal health and personalized medicine; ambient assisted living technologies; innovative implantable miniaturized sensors and actuators; smart spaces for elderly and impaired users;

Chair: Tim Güneysu, University of Bremen, DE, Contact

Co-Chair: Wieland Fischer, Infineon, DE, Contact

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Design experiences on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random number generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including Physically Unclonable Functions, and more.

Chair: , Contact

Co-Chair: Christian Weis, University of Kaiserslautern, DE, Contact

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Design experiences in the area of reliable and variability-aware adaptive systems for practical and industrial applications. The scope of this topic includes, but is not limited to, reliable and reconfigurable system development and optimization, practical application mechanisms and use cases that compensate reliability issues, such as aging, variability and temperature, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

Chair: Andy M. Tyrrell, University of York, GB, Contact

Co-Chair: Yu Wang, Tsinghua University, CN, Contact

Topic Members (click to open)

Applications of and design methods for systems based on future and emerging technologies including: biologically-based or biologically-inspired computing systems; Bio-MEMS, lab-on-a-chip; emerging models of computation (e.g., quantum computing, reversible logic, approximate computing, stochastic computing); application case studies for emerging technologies (e.g., cryptography, wearable computing, e-textiles, energy-critical etc.)

Chair: Raphaël David, CEA LIST, FR, Contact

Co-Chair: Eugenio Villar, University of Cantabria, ES, Contact

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Short 2-page industrial papers are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.

Chair: Mehdi Tahoori, Karlsruhe Institute of Technology (KIT), DE, Contact

Co-Chair: Said Hamdioui, Delft University of Technology, NL, Contact

Topic Members (click to open)

Identification, characterization and modeling of defects, faults and degradation mechanisms in conventional, advanced and emerging technologies (FinFET, FDSOI, TSV, Memristor, MTJ, CNT…); defect-based fault analysis; reliability analysis and modeling at device, circuit and component level; process yield modeling and enhancement; design-for-manufacturability and design-for-yield; noise and uncertainty modeling at circuit and component level; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations at circuit and component level;

Chair: Wu-Tung Cheng, Mentor Graphics, US, Contact

Co-Chair: M. Sonza Reorda, Politecnico di Torino, IT, Contact

Topic Members (click to open)

Algorithms for test pattern generation (TPG); TPG for delay and small-delay faults; TPG for low power; Algorithms for test compression and compaction; ATPGs; Fault simulation; Diagnosis; Power Issues in Testing; Test generation for: Microprocessors, Memories, FPGAs and regular structures; Algorithms for board and system test; Volume diagnosis and yield analysis

Chair: Sybille Hellebrand, University of Paderborn, DE, Contact

Co-Chair: Ozgur Sinanoglu, New York University - Abu Dhabi, AE, Contact

Topic Members (click to open)

Architectures and solutions for design for test, diagnosis, debug, post silicon validation; BIST and embedded test; Power-On Self-Test; Test architectures and infrastructures for memories, FPGAs, 2.5D, 3D, SiP, NoC, Microprocessors; Test Infrastructures for Secure Devices; Test principles and methods for design-for-trust; ATE architectures; Test Standards (JTAG, IJTAG, 1500, P1838)

Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

Co-Chair: Jaume Abella, Barcelona Supercomputing Center, ES, Contact

Topic Members (click to open)

Fault models: Permanent, Transient and Soft Errors; Dependability Evaluation; Space-, Time- and Information-redundancy based dependability solutions; Highly-Available Systems; Reliable, Secure and Fail-Safe System Design; HW/SW solutions for on-line fault detection, tolerance, recovery and aging mitigation; Countermeasures Against Fault Attacks.

Chair: André Ivanov, , CA, Contact

Co-Chair: Georges Gielen, Katholieke Universiteit Leuven, BE, Contact

Topic Members (click to open)

Layout and topology generation; architecture, system and circuit synthesis and optimization; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; MEMS; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.

Chair: Rodolfo Pellizzoni, University of Waterloo, CA, Contact

Co-Chair: Kai Lampka, Elektrobit Automotive GmbH, DE, Contact

Topic Members (click to open)

Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; software for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications.

Chair: Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact

Co-Chair: Aviral Shrivastava, Arizona State University, US, Contact

Topic Members (click to open)

Compiler support for multi-core/many-core architectures, GPUs, CGRAs, FPGAs, accelerators in heterogeneous computing platforms, memory hierarchy including caches, scratchpad, and non-volatile memories; Code analysis, optimization, and generation for different metrics (e.g., performance, power/energy, code/data size, reliability, security, WCET, etc.); Just-in-time compilation, interpreters, binary translation; Compiler support for enhanced debugging, profiling, and traceability; Software tools and techniques for design space exploration (compilers, simulators, synthesis tools); Compilation infrastructures for high-level synthesis and domain-specific or streaming languages for embedded systems; Software synthesis for IoT, wearables, cyber-physical systems, programmable microfluidics.

Chair: Petru Eles, Linköping University, SE, Contact

Co-Chair: Alain Girault, INRIA, FR, Contact

Topic Members (click to open)

Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components. Monitoring and run-time verification of embedded systems.

Chair: Hiroyuki Tomiyama, Ritsumeikan University, JP, Contact

Co-Chair: Akash Kumar, Technische Universitaet Dresden, DE, Contact

Topic Members (click to open)

Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; Virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; Software support for approximate computation and accelerators; Software architectures for low power and temperature awareness.

Chair: Paul Pop, Technical University of Denmark, DK, Contact

Co-Chair: Karl-Erik Arzen, Lund University, SE, Contact

Topic Members (click to open)

Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); Modeling techniques for large-scale cyber physical systems design and analysis; Verification and validation in CPS; Safety and cybersecurity in CPS systems; Internet of things and CPS: modeling, analysis, and design; Software-intensive CPS; Data-mining and CPS; Autonomous and semi-autonomous large-scale CPS and related issues; Socio-technical systems (ex. empowered consumer and organizational behavior in smart grids) and CPS; Cognitive control for CPS; Modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis