UB08 Session 8

Label	Presentation Title Authors
UB08.1	AHLS_DESYNC: DESYNCHRONIZATION TOOL FOR HIGH-LEVEL SYNTHESIS OF ASYNCHRONOUS CIRCUITS Presenter: Jean Simatic, TIMA Laboratory, FR Authors: Jean Simatic, Rodrigo Possamai Bastos and Laurent Fesquet, TIMA Laboratory, FR Abstract We present a tool for the high-level synthesis (HLS) of event-driven (asynchronous) circuits. Our approach first uses an existing HLS tool, AUGH, to generate a synchronous finite state machine (FSM) and a data-path. Then, the presented tool desynchronizes solely the FSM in 5 steps: 1. Parse the FSM to build a state graph containing the control signal assignments. 2. Separate multiplexer control and register control signals by analyzing the data-path. 3. Generate an event-driven FSM netlist by mapping the state graph on a dedicated set of asynchronous controllers. 4. Synthesize the data-path thanks to a commercial synthesis tool (Design Compiler). 5. Estimate the delays in the data-path with a static timing analysis tool (PrimeTime). Insert delays in the controller accordingly. Our demonstration will exhibit two testbenches: a GCD algorithm to expose the basic concepts and a non-uniform sampling FIR filter more representative of real-life applications. Download Paper (PDF)
UB08.2	GRIP: GRAPH-REWRITING-BASED IP-INTEGRATION (GRIP) - AN EDA TOOL FOR SOFTWARE DEFINED SOC DESIGN Presenter: Munish Jassi, Technische Universität München, DE Authors: Munish Jassi, Yong Hu, Jian Lyu, Daniel Mueller-Gritschneder and Ulf Schlichtmann, Technische Universität München, DE Abstract The GRIP tool - Graph-Rewriting-Based IP-Integration - provides system engineers with a comprehensive platform that takes care of their IP-integration concerns for IP-centric SoC designs, also referred to as SW-defined SoCs. The tool uses the standardized meta-data IP-XACT format for HW descriptions and encodes the design IP-integration knowledge as a set of integration rules based on graph rewriting and grammar theory. The tool automates and encodes the step-by-step integration of IPs to build a desired system architecture. Multiple sequential IP-integration steps can be compiled to iteratively generate new architectures. For design space exploration (DSE), constraints can be given to generate a desired subset of candidate SoCs. Code generation generates the design files for each architecture. This is demonstrated as DSE for OpenCV CV application running on a Xilinx Zynq chipset based Zedboard. GRIP additionally generates the HW-drivers for both non-OS and Linux-based systems. Download Paper (PDF)
UB08.3	CLASH: DIGITAL CIRCUITS IN CλASH Presenter: Christiaan Baaij, University of Twente, NL Authors: Christiaan Baaij and Jan Kuper, University of Twente, NL Abstract CλaSH is a novel compiler system for generating digital circuits as described by a mathematical/functional specification of the architecture. We will demonstrate several applications written in CλaSH: * Tunneling ball device: With a minimal amount of acceleration, a fast spinning metal disk is either sped up or slowed down so that a falling ball can fall through one of the metal disk's two holes. * Music synthesizer and spectrum analyser: An audio CODEC samples music being played from either an MP3 player or a computer. We can apply several digital filters which affect the music. The effects of these filters can be both seen on a monitor, and heard through speakers connected to the FPGA board. * Multi-processor system: The system is used in a compiler construction course, where the compiler is written in the Haskell. Because CλaSH is proper subset of Haskell, students can build and experiment with the compiler and the multi-processor system in the same environment. Download Paper (PDF)
UB08.5	LISA: ENABLING LAYERED INTEROPERABILITY FOR INTERNET OF THINGS THROUGH LISA Presenter: Behailu Shiferaw Negash, University of Turku, FI Authors: Behailu Shiferaw Negash¹, Amir-Mohammad Rahmani¹, Tomi Westerlund¹, Pasi Liljeberg¹ and Hannu Tenhunen² ¹University of Turku, FI; ²University of Turku, FI and Royal Institute of Technology (KTH), SE Abstract There is high expectation towards the changes that come with the implementation of the Internet of Things (IoT). However, this vision is limited by the heterogeneous nature of IoT devices. This led to vertical application silos that are incapable of working together. To ease this problem of heterogeneity, we have developed a lightweight interoperability framework, LISA, to hide variations in communication technology and data formats and provide a uniform API for programmers. LISA is inspired by Network on Terminal Architecture (NoTA), an open framework from Nokia Research Center. There are few frameworks for interoperability of IoT. However, these frameworks fail to address the resource limitations of the majority of IoT devices. To the best of our knowledge, LISA is the first framework designed for resource constrained devices. This demonstration shows LISA in action, helping heterogeneous devices interoperate through a gateway in the fog layer between the devices and the cloud. Download Paper (PDF)
UB08.6	MCC: CONTRACT-BASED AUTOMATED INTEGRATION FOR COMPONENT-BASED CRITICAL SYSTEMS Presenter: Johannes Schlatow, TU Braunschweig, DE Authors: Johannes Schlatow, Marcus Nolte, Rolf Ernst and Markus Maurer, TU Braunschweig, DE Abstract In the scope of the research unit Controlling Concurrent Change, we developed a contract-based middleware to autonomously manage and ensure the safety, availability and security properties of a component-based run-time environment. It guarantees that any change to the system is formally analysed beforehand and only applied if it does not violate any of the contracts, thereby enabling in-field updateability of complex critical systems. For this purpose, a Multi-Change Controller (MCC) aggregates component contracts and invokes viewpoint-specific analysis engines to evaluate change requests and find feasible system configurations. The MCC is specifically designed for extensibility so that analysis engines can be added and combined dependent on the application domain. We show a demonstrator that showcases and illustrates this contract-based process for an automated integration of an automotive system. Our demonstrator is built upon the Genode OS Framework and Xilinx Zynq-7000 SoCs. Download Paper (PDF)
UB08.7	SRAM-BASED PHYSICAL UNCLONABLE KEYS FOR BLE SMART LOCK SYSTEMS Presenters: Iluminada Baturone and Miguel Ángel Prada-Delgado, University of Seville, ES Authors: Iluminada Baturone, Miguel Ángel Prada-Delgado, Alfredo Vázquez-Reyes, Laurentiu Acasandrei, Diego Fernández-Barrera and Javier Prada-Delgado, Abstract Nowadays, several smart lock systems use Bluetooth Low Energy (BLE) to recognize when a smartphone, conveniently authenticated by a digital key, is near. The keys can be shared and are managed by web apps, so that system security depends on how the software prevents an attacker from discovering the keys. In order to increase security by a two-factor method ('something you have' in addition to 'something you know'), the BLE smart lock system prototype shown in this demonstrator recognizes when a user wearing an authenticated BLE chip (in a key fob, wristband, etc.) is near. The digital keys are not stored but they are regenerated on the fly by only the trusted chip. This is possible by using the start-up values of the SRAM in the BLE chip, which act as a physical unclonable function (PUF), so that the chip cannot be cloned. The SRAM start-up values of the BLE chip are also exploited as true random numbers to derive fresh keys for each transaction with the lock. Download Paper (PDF)
UB08.8	CONTREP: A SINGLE-SOURCE FRAMEWORK FOR UML-BASED MODELLING AND DESIGN OF MIXED-CRITICALITY SYSTEMS Presenter: Fernando Herrera, University of Cantabria, ES Authors: Fernando Herrera and Eugenio Villar, University of Cantabria, ES Abstract Mixed-criticality systems integrate applications, platform resources and requirements with different criticality. A criticality reflects the impact of either a failure of a component or a violation of a requirement, which can range from irrelevant to catastrophic effects. This booth presents the CONTREP framework, which supports UML/MARTE based modeling, analysis and design of mixed-criticality embedded systems. The booth shows a model of a quadcopter control system which integrates safety critical (e.g. flight control), mission-critical (e.g., a video processing payload), and non-critical (e.g., monitoring) functions. The booth shows how mixed-criticality is captured, together with the description of the functional architecture, and of the multi-core embedded platform where the system is implemented; how CONTREP automates different design activities, i.e. model validation, performance assessment and design space exploration, exploiting mixed-criticality information in every case. Download Paper (PDF)
UB08.9	CHIMPANC: CHANGE MANAGEMENT USING CHIMPANC Presenter: Jannis Stoppe, DFKI and University of Bremen, DE Authors: Jannis Stoppe, Martin Ring and Rolf Drechsler, DFKI and University of Bremen, DE Abstract One approach to remedy the issue of increasing complexity in the hardware design process is to provide designers with more abstract languages that allow systems to be designed top-down, starting with an abstract model of the system and its requirements. Several of these languages such as SysML and SystemC are being used today. We propose the Change Impact Analysis and Control Tool (ChImpAnC) to handle these challenges. ChImpAnC extracts the relevant information from the models on the different levels and constructs mappings between them, thus allowing to check consistency and refinements, and moreover calculating the impact of changes. Thus, ChImpAnC ensures that e.g. a written specification or documentation is not made obsolete by changes in the implementation without being warned about it. Download Paper (PDF)
UB08.10	LLBMC / QPR-VERIFY: HIGH-PRECISION BOUNDED MODEL CHECKING FOR AUTOMOTIVE SOFTWARE Presenter: Carsten Sinz, Karlsruhe Institute of Technology (KIT), DE Authors: Carsten Sinz, David Farago, Florian Merz and Reimo Schaupp, Karlsruhe Institute of Technology (KIT), DE Abstract LLBMC (the low-level bounded model checker) is a static software analysis tool for finding bugs in C (and, to some extent, in C++) programs. It is mainly intended for checking low-level system code and is based on the technique of Bounded Model Checking. LLBMC is fully automatic and requires minimal preparation efforts and user interaction. It supports all C constructs, including not so common features such as bitfields. LLBMC models memory accesses (heap, stack, global variables) with high precision and is thus able to find hard-to-detect memory access errors like heap or stack buffer overflows. LLBMC can also uncover errors due to uninitalized variables or other sources of non-deterministic behavior. Due to its precise analysis, LLBMC produces almost no false alarms (false positives). LLBMC is developed at Karlsruhe Institute of Technology, and will soon be commercially available via a university spin-off, QPR Technologies. Download Paper (PDF)
18:00	End of session

Label

Presentation Title
Authors

UB08.1

AHLS_DESYNC: DESYNCHRONIZATION TOOL FOR HIGH-LEVEL SYNTHESIS OF ASYNCHRONOUS CIRCUITS
Presenter:
Jean Simatic, TIMA Laboratory, FR
Authors:
Jean Simatic, Rodrigo Possamai Bastos and Laurent Fesquet, TIMA Laboratory, FR
Abstract
We present a tool for the high-level synthesis (HLS) of event-driven (asynchronous) circuits. Our approach first uses an existing HLS tool, AUGH, to generate a synchronous finite state machine (FSM) and a data-path. Then, the presented tool desynchronizes solely the FSM in 5 steps: 1. Parse the FSM to build a state graph containing the control signal assignments. 2. Separate multiplexer control and register control signals by analyzing the data-path. 3. Generate an event-driven FSM netlist by mapping the state graph on a dedicated set of asynchronous controllers. 4. Synthesize the data-path thanks to a commercial synthesis tool (Design Compiler). 5. Estimate the delays in the data-path with a static timing analysis tool (PrimeTime). Insert delays in the controller accordingly. Our demonstration will exhibit two testbenches: a GCD algorithm to expose the basic concepts and a non-uniform sampling FIR filter more representative of real-life applications.
Download Paper (PDF)

UB08.2

GRIP: GRAPH-REWRITING-BASED IP-INTEGRATION (GRIP) - AN EDA TOOL FOR SOFTWARE DEFINED SOC DESIGN
Presenter:
Munish Jassi, Technische Universität München, DE
Authors:
Munish Jassi, Yong Hu, Jian Lyu, Daniel Mueller-Gritschneder and Ulf Schlichtmann, Technische Universität München, DE
Abstract
The GRIP tool - Graph-Rewriting-Based IP-Integration - provides system engineers with a comprehensive platform that takes care of their IP-integration concerns for IP-centric SoC designs, also referred to as SW-defined SoCs. The tool uses the standardized meta-data IP-XACT format for HW descriptions and encodes the design IP-integration knowledge as a set of integration rules based on graph rewriting and grammar theory. The tool automates and encodes the step-by-step integration of IPs to build a desired system architecture. Multiple sequential IP-integration steps can be compiled to iteratively generate new architectures. For design space exploration (DSE), constraints can be given to generate a desired subset of candidate SoCs. Code generation generates the design files for each architecture. This is demonstrated as DSE for OpenCV CV application running on a Xilinx Zynq chipset based Zedboard. GRIP additionally generates the HW-drivers for both non-OS and Linux-based systems.
Download Paper (PDF)

UB08.3

CLASH: DIGITAL CIRCUITS IN CλASH
Presenter:
Christiaan Baaij, University of Twente, NL
Authors:
Christiaan Baaij and Jan Kuper, University of Twente, NL
Abstract
CλaSH is a novel compiler system for generating digital circuits as described by a mathematical/functional specification of the architecture. We will demonstrate several applications written in CλaSH: * Tunneling ball device: With a minimal amount of acceleration, a fast spinning metal disk is either sped up or slowed down so that a falling ball can fall through one of the metal disk's two holes. * Music synthesizer and spectrum analyser: An audio CODEC samples music being played from either an MP3 player or a computer. We can apply several digital filters which affect the music. The effects of these filters can be both seen on a monitor, and heard through speakers connected to the FPGA board. * Multi-processor system: The system is used in a compiler construction course, where the compiler is written in the Haskell. Because CλaSH is proper subset of Haskell, students can build and experiment with the compiler and the multi-processor system in the same environment.
Download Paper (PDF)

UB08.5

LISA: ENABLING LAYERED INTEROPERABILITY FOR INTERNET OF THINGS THROUGH LISA
Presenter:
Behailu Shiferaw Negash, University of Turku, FI
Authors:
Behailu Shiferaw Negash¹, Amir-Mohammad Rahmani¹, Tomi Westerlund¹, Pasi Liljeberg¹ and Hannu Tenhunen²
¹University of Turku, FI; ²University of Turku, FI and Royal Institute of Technology (KTH), SE
Abstract
There is high expectation towards the changes that come with the implementation of the Internet of Things (IoT). However, this vision is limited by the heterogeneous nature of IoT devices. This led to vertical application silos that are incapable of working together. To ease this problem of heterogeneity, we have developed a lightweight interoperability framework, LISA, to hide variations in communication technology and data formats and provide a uniform API for programmers. LISA is inspired by Network on Terminal Architecture (NoTA), an open framework from Nokia Research Center. There are few frameworks for interoperability of IoT. However, these frameworks fail to address the resource limitations of the majority of IoT devices. To the best of our knowledge, LISA is the first framework designed for resource constrained devices. This demonstration shows LISA in action, helping heterogeneous devices interoperate through a gateway in the fog layer between the devices and the cloud.
Download Paper (PDF)

UB08.6

MCC: CONTRACT-BASED AUTOMATED INTEGRATION FOR COMPONENT-BASED CRITICAL SYSTEMS
Presenter:
Johannes Schlatow, TU Braunschweig, DE
Authors:
Johannes Schlatow, Marcus Nolte, Rolf Ernst and Markus Maurer, TU Braunschweig, DE
Abstract
In the scope of the research unit Controlling Concurrent Change, we developed a contract-based middleware to autonomously manage and ensure the safety, availability and security properties of a component-based run-time environment. It guarantees that any change to the system is formally analysed beforehand and only applied if it does not violate any of the contracts, thereby enabling in-field updateability of complex critical systems. For this purpose, a Multi-Change Controller (MCC) aggregates component contracts and invokes viewpoint-specific analysis engines to evaluate change requests and find feasible system configurations. The MCC is specifically designed for extensibility so that analysis engines can be added and combined dependent on the application domain. We show a demonstrator that showcases and illustrates this contract-based process for an automated integration of an automotive system. Our demonstrator is built upon the Genode OS Framework and Xilinx Zynq-7000 SoCs.
Download Paper (PDF)

UB08.7

SRAM-BASED PHYSICAL UNCLONABLE KEYS FOR BLE SMART LOCK SYSTEMS
Presenters:
Iluminada Baturone and Miguel Ángel Prada-Delgado, University of Seville, ES
Authors:
Iluminada Baturone, Miguel Ángel Prada-Delgado, Alfredo Vázquez-Reyes, Laurentiu Acasandrei, Diego Fernández-Barrera and Javier Prada-Delgado,
Abstract
Nowadays, several smart lock systems use Bluetooth Low Energy (BLE) to recognize when a smartphone, conveniently authenticated by a digital key, is near. The keys can be shared and are managed by web apps, so that system security depends on how the software prevents an attacker from discovering the keys. In order to increase security by a two-factor method ('something you have' in addition to 'something you know'), the BLE smart lock system prototype shown in this demonstrator recognizes when a user wearing an authenticated BLE chip (in a key fob, wristband, etc.) is near. The digital keys are not stored but they are regenerated on the fly by only the trusted chip. This is possible by using the start-up values of the SRAM in the BLE chip, which act as a physical unclonable function (PUF), so that the chip cannot be cloned. The SRAM start-up values of the BLE chip are also exploited as true random numbers to derive fresh keys for each transaction with the lock.
Download Paper (PDF)

UB08.8

CONTREP: A SINGLE-SOURCE FRAMEWORK FOR UML-BASED MODELLING AND DESIGN OF MIXED-CRITICALITY SYSTEMS
Presenter:
Fernando Herrera, University of Cantabria, ES
Authors:
Fernando Herrera and Eugenio Villar, University of Cantabria, ES
Abstract
Mixed-criticality systems integrate applications, platform resources and requirements with different criticality. A criticality reflects the impact of either a failure of a component or a violation of a requirement, which can range from irrelevant to catastrophic effects. This booth presents the CONTREP framework, which supports UML/MARTE based modeling, analysis and design of mixed-criticality embedded systems. The booth shows a model of a quadcopter control system which integrates safety critical (e.g. flight control), mission-critical (e.g., a video processing payload), and non-critical (e.g., monitoring) functions. The booth shows how mixed-criticality is captured, together with the description of the functional architecture, and of the multi-core embedded platform where the system is implemented; how CONTREP automates different design activities, i.e. model validation, performance assessment and design space exploration, exploiting mixed-criticality information in every case.
Download Paper (PDF)

UB08.9

CHIMPANC: CHANGE MANAGEMENT USING CHIMPANC
Presenter:
Jannis Stoppe, DFKI and University of Bremen, DE
Authors:
Jannis Stoppe, Martin Ring and Rolf Drechsler, DFKI and University of Bremen, DE
Abstract
One approach to remedy the issue of increasing complexity in the hardware design process is to provide designers with more abstract languages that allow systems to be designed top-down, starting with an abstract model of the system and its requirements. Several of these languages such as SysML and SystemC are being used today. We propose the Change Impact Analysis and Control Tool (ChImpAnC) to handle these challenges. ChImpAnC extracts the relevant information from the models on the different levels and constructs mappings between them, thus allowing to check consistency and refinements, and moreover calculating the impact of changes. Thus, ChImpAnC ensures that e.g. a written specification or documentation is not made obsolete by changes in the implementation without being warned about it.
Download Paper (PDF)

UB08.10

LLBMC / QPR-VERIFY: HIGH-PRECISION BOUNDED MODEL CHECKING FOR AUTOMOTIVE SOFTWARE
Presenter:
Carsten Sinz, Karlsruhe Institute of Technology (KIT), DE
Authors:
Carsten Sinz, David Farago, Florian Merz and Reimo Schaupp, Karlsruhe Institute of Technology (KIT), DE
Abstract
LLBMC (the low-level bounded model checker) is a static software analysis tool for finding bugs in C (and, to some extent, in C++) programs. It is mainly intended for checking low-level system code and is based on the technique of Bounded Model Checking. LLBMC is fully automatic and requires minimal preparation efforts and user interaction. It supports all C constructs, including not so common features such as bitfields. LLBMC models memory accesses (heap, stack, global variables) with high precision and is thus able to find hard-to-detect memory access errors like heap or stack buffer overflows. LLBMC can also uncover errors due to uninitalized variables or other sources of non-deterministic behavior. Due to its precise analysis, LLBMC produces almost no false alarms (false positives). LLBMC is developed at Karlsruhe Institute of Technology, and will soon be commercially available via a university spin-off, QPR Technologies.
Download Paper (PDF)

18:00

End of session

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