Technical Programme Committee 2015

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TPC Meeting

For detailed information about the DATE 2015 TPC meeting, please visit the event’s website at: http://date2015tpc.epfl.ch/

For a short description of the DATE 2015 TPC meeting, agenda of the meeting and registration information, please click here

Track D: Design, Methods and Tools (click to open)

addressing design automation, design tools and hardware architectures for electronic and embedded systems. Emphasis is on methods, algorithms and tools related to the use of computers in designing complete systems. This includes significant improvements on existing design methods and tools as well as forward-looking approaches to model and design future system architectures, design flows and environments.

Track Chair: David Atienza, EPFL, CH, Contact

Topics

D1 System Specification and Modeling (click to open)

Chair: Christian Haubelt, University of Rostock, DE, Contact

Co-Chair: Andy Pimentel, University of Amsterdam, NL, Contact

Topic Members (click to open)

  • Andreas Gerstlauer, University of Texas at Austin, US, Contact
  • Timo Hämäläinen, Tampere University of Technology, FI, Contact
  • Jorn W. Janneck, Lund University, SE, Contact
  • Wolfgang Mueller, Universität Paderborn, DE, Contact
  • Frank Oppenheimer, OFFIS e. V., DE, Contact
  • Gianluca Palermo, Politecnico di Milano, IT, Contact
  • Francois Pecheux, UPMC/LIP6, FR, Contact
  • Laurence Pierre, TIMA, FR, Contact
  • Ingo Sander, Royal Institute of Technology, SE, Contact
  • Leandro Soares Indrusiak, University of York, GB, Contact
  • Sander Stuijk, Eindhoven University of Technology, NL, Contact

Modeling and specification methodologies for complex HW-SW systems; (formal) models of computation and their (static) analysis; modeling and analysis of functional and non-functional system properties; concurrency models; multi-domain/multi-criteria specifications and models; application and workload models; requirements engineering; system-level modeling and simulation of multi- and many-core SoCs; Transaction Level Modeling (TLM) and model refinement; modeling of system adaptivity; system modeling and specification languages; model-driven engineering; meta-modeling; executable specifications; specification driven design and validation flows.

D2 System Design, High-Level Synthesis and Optimization (click to open)

Chair: Andreas Herkersdorf, TU München, DE, Contact

Co-Chair: Nikil Dutt, Unviersity of California, Irvine, US, Contact

Topic Members (click to open)

  • Kubilay Atasu, IBM Research, CH, Contact
  • Alberto A. Barrio del, Universidad Complutense de Madrid: UCM, ES, Contact
  • Lars Bauer, KIT, DE, Contact
  • Philippe Coussy, Universite de Bretagne Sud / Lab-STICC, FR, Contact
  • Kim Grüttner, OFFIS - Institute for Information Technology, DE, Contact
  • Soonhoi Ha, Seoul National University, KR, Contact
  • Yuko Hara-Azumi, Tokyo Institute of Technology, JP, Contact
  • Dirk Koch, University of Manchester, GB, Contact
  • Luciano Lavagno, Politecnico di Torino, IT, Contact
  • Roman Lysecky, University of Arizona, US, Contact
  • Jan Madsen, Technical University of Denmark, DK, Contact
  • Brett Meyer, McGill University, CA, Contact
  • Christian Plessl, University of Paderborn, DE, Contact
  • Donatella Sciuto, Politecnico di Milano, It, Contact
  • Todor Stefanov, Leiden University, NL, Contact
  • Jürgen Teich, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact
  • David Thomas, Imperial College London, GB, Contact
  • Yosinori Watanabe, Cadence Design Systems, US, Contact
  • Jason Xue Chun, City University of Hong Kong, HK, Contact
  • Daniel Ziener, FAU Erlangen, DE, Contact

High-level and system-level synthesis techniques; high-level design languages; system-level models for design and optimization; methods for hardware/software co-design and partitioning; control and data flow analysis; hardware/software interface and protocol communication synthesis; interface-based and correct-by-construction designs; high-level and system-level scheduling, allocation and binding techniques; multi-objective optimization techniques (performance, power, reliability, security) for high-level and system design; platform-based and reuse-centric design methods and architectures; hw/sw design patterns for multi-core system on chip (MPSoC) and distributed, networked embedded systems; system-level design of heterogeneous computing systems.

D3 System Simulation and Validation (click to open)

Chair: Prabhat Mishra, University of Florida, US, Contact

Co-Chair: Elena Vatajelu, Politecnico de Torino, IT, Contact

Topic Members (click to open)

  • Valeria Bertacco, University of Michigan, US, Contact
  • Mingsong Chen, East China Normal University, CN, Contact
  • Pallab Dasgupta, Indian Institute of Technology Kharagpur, IN, Contact
  • Adrian Evans, Iroc, FR, Contact
  • Franco Fummi, Universita' di Verona, IT, Contact
  • Rand Gray, Intel Corporation, US, Contact
  • Daniel Grosse, Solvertec GmbH, DE, Contact
  • Michael Hsiao, Virginia Tech, US, Contact
  • Florian Letombe, Synopsys, FR, Contact
  • Ronny Morad, IBM Research - Haifa, IL, Contact
  • Xiaoke Qin, NVIDIA, US, Contact
  • Jaan Raik, Tallinn University of Technology, EE, Contact
  • Pablo Sanchez, University of Cantabria, ES, Contact
  • Alper Sen, Bogazici University, TR, Contact
  • Andreas Veneris, University of Toronto, CA, Contact
  • Li Wang, UC Santa Barbara, US, Contact

Simulation-based verification; hardware/software co-simulation and validation; transaction-level validation; advanced simulation and emulation techniques from system to circuit level; simulation accelerators; testbench generation for functional validation; multi-domain simulation techniques; validation of cyber-physical systems, SoCs and emerging architectures.

D4 Formal Methods and System Verification (click to open)

Chair: Jason Baumgartner, IBM Corporation, US, Contact

Co-Chair: Julien Schmaltz, Eindhoven University of Technology, NL, Contact

Topic Members (click to open)

  • Armin Biere, Universitaet Linz, AT, Contact
  • Per Bjesse, Synopsys, IE, Contact
  • Gianpiero Cabodi, Politecnico di Torino, IT, Contact
  • Alessandro Cimatti, FBK-irst (Fondazione Bruno Kessler - Center for Information technology), IT, Contact
  • Barbara Jobstmann, VERIMAG, FR, Contact
  • Katell Morin-Allory, TIMA Laboratory, FR, Contact
  • Christoph Scholl, University Freiburg, DE, Contact
  • Daryl Stewart, ARM, GB, Contact

Formal verification and specification techniques (including equivalence checking, model checking, symbolic simulation, theorem proving, abstraction and decomposition techniques); technologies supporting formal verification; semi-formal verification techniques; formal verification of IPs, SoCs, cores, real-time and embedded systems; integration of verification into design flows; challenges of multi-cores, both as verification targets and as verification host platforms.

DT5 Design and Test for Analog and Mixed-Signal Systems and Circuits (click to open)

Chair: Günhan Dündar, Boğaziçi University, TR, Contact

Co-Chair: haralampos [dot] stratigopoulos at lip6 [dot] fr, Contact

Topic Members (click to open)

  • Florence Azais, LIRMM (CNRS - Univ. Montpellier II), FR, Contact
  • Abhijit Chatterjee, Georgia Tech, US, Contact
  • Catherine Dehollain, EPFL, CH, Contact
  • Francisco Fernandez, IMSE, CSIC and University of Sevilla, ES, Contact
  • Georges Gielen, Katholieke Universiteit Leuven, BE, Contact
  • Helmut Graeb, Technische Universitaet Muenchen, DE, Contact
  • Christoph Grimm, TU Vienna, AT, Contact
  • Lars Hedrich, University of Frankfurt, DE, Contact
  • Nuno Horta, Instituto de Telecomunicações, Instituto Superior Técnico – TU Lisbon, PT, Contact
  • Andre Ivanov, UBC, CA, Contact
  • Tom Kazmierski, University of Southampton, GB, Contact
  • Gildas Leger, IMSE-CNM-CSIC, ES, Contact
  • Dominique MORCHE, CEA-Leti, FR, Contact

Layout and topology generation; architecture and system synthesis; formal and symbolic techniques; hardware description languages for AMS circuits and systems; models of computation; innovative circuit topologies and architectures; modeling strategies for complex analogue, mixed signal or mixed-domain systems; self-healing and self- calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for- manufacturability and design-for-yield; test metrics and economics.

D6 Emerging Technologies and Systems (click to open)

Chair: Michael Niemier, University Of Notre Dame, US, Contact

Co-Chair: Ian O'Connor, Lyon Institute of Nanotechnology, FR, Contact

Topic Members (click to open)

  • Krishnendu Chakrabarty, Duke University, US, Contact
  • Pierre-Emmanuel Gaillardon, EPFL, CH, Contact
  • Swaroop Ghosh, University of South Florida, US, Contact
  • Tsung-Yi Ho, National Cheng Kung University, TW, Contact
  • Jacques-Olivier Klein, IEF - Univ. Paris Sud, FR, Contact
  • Smita Krishnaswamy, Columbia Univ, US, Contact
  • Dmitri Maslov, National Science Foundation, US, Contact
  • Subhasish Mitra, Stanford University, US, Contact
  • Kartik Mohanram, University of Pittsburgh, US, Contact
  • Marco Ottavi, University of Rome "Tor Vergata", IT, Contact
  • Ilia Polian, University of Passau, DE, Contact
  • Jack Sampson, Pennsylvania State University, US, Contact
  • Guangyu Sun, Peking University, CN, Contact
  • Yvain Thonnart, CEA, LETI, MINATEC, FR, Contact
  • Aida Todri-Sanial, CNRS - LIRMM, FR, Contact
  • Andy M. Tyrrell, University of York, GB, Contact
  • Chun-Yao Wang, National Tsing Hua University, TW, Contact
  • Yu Wang, Tsinghua University, CN, Contact

Modeling, circuit design, system architectures and design automation flows for future technologies: 3D integration, MEMS, non-CMOS logic, memory and interconnect, emerging FET devices, etc. System design methods and models of computation for emerging applications: lab-on-a-chip, biologically-based or -inspired computing systems, quantum computing, reversible logic, etc.

D7 Power Modeling, Optimization and Low-Power Design (click to open)

Chair: Martino Ruggiero, Wispes, IT, Contact

Co-Chair: Marisa Lopez-Vallejo, UPM, ES, Contact

Topic Members (click to open)

  • Antonio Acosta, Univ. of Seville/IMSE, ES, Contact
  • Edith Beigne, CEA-Leti Minatec, FR, Contact
  • Luca Benini, ETHZ, CH, Contact
  • Naehyuck Chang, Seoul National University, KR, Contact
  • Alberto Garcia-Ortiz, Univ. Bremen, DE, Contact
  • Domenik Helms, OFFIS, DE, Contact
  • Ruzica Jevtic, Univ. Carlos III, ES, Contact
  • Alberto Macii, Politecnico di Torino, IT, Contact
  • Diana Marculescu, Carnegie Mellon University, US, Contact
  • Andrea Marongio, Univ. of Bologna, IT, Contact
  • Vijaykrishnan Narayanan, Pennsylvania State University, US, Contact
  • Seda Memik, Northwestern University, US, Contact
  • Fernando Rincón, UCLM, ES, Contact
  • Tajana Simunic Rosing, UCSD, US, Contact
  • Marian Verhelst, KULeuven - ESAT - MICAS, BE, Contact

Algorithms, techniques and tools for power modeling, estimation and optimization of electronic systems applicable at all levels of the design, including both hardware and software; dynamic power management and leakage currents minimization; design flows and circuit architectures for ultra-low power consumption. Energy harvesting and battery modeling and design.

D8 Network on Chip (click to open)

Chair: Fabien Clermidy, CEA-Leti, FR, Contact

Co-Chair: Steven Nowick, Columbia University, US, Contact

Topic Members (click to open)

  • Federico Angiolini, iNoCs, CH, Contact
  • Davide Bertozzi, University of Ferrara, IT, Contact
  • Luca Carloni, Columbia University, US, Contact
  • Koushik Chakraborty, Utah State University, US, Contact
  • Masoud Daneshtalab, UTU, FI, Contact
  • Georgios Dimitrakopoulos, Democritus University of Thrace (DUTH), GR, Contact
  • Josè Flich, Universidad Politecnica de Valencia, ES, Contact
  • Paul Gratz, Texas A&M University, US, Contact
  • Andreas Hansson, ARM Ltd, GB, Contact
  • Shaahin Hessabi, Sharif University of Technology, IR, Contact
  • Jung Ho Ahn, Seoul National University, KR, Contact
  • John Kim, KAIST, KR, Contact
  • Sébastien Le Beux, Lyon Institute of Nanotechnology, FR, Contact
  • , Contact
  • Hiroki Matsutani, Keio University, JP, Contact
  • Umit Ogras, Arizona State University, US, Contact

Architecture and modeling techniques for NoC; Design methodologies and architectures for on-chip interconnection networks: topology, switching, routing and flow control; NoC service frameworks for Quality of Service, security, power management and fault tolerance; Techniques and methodologies for NoC testing; GALS and asynchronous architectures for NoCs; Integration of external interfaces/memory controllers with NoCs; Cache-coherent NoCs; hardware/software communication abstraction, component-based modeling, platform-based design and methodologies, NoC design space exploration frameworks; Programming models for NoC-based platforms; design of NoCs targeting alternative technologies (photonics/optics, wireless, 3D stacking, etc.).

D9 Architectural and Microarchitectural Design (click to open)

Chair: Todd Austin, University of Michigan, US, Contact

Co-Chair: Cristina Silvano, Politecnico di Milano, IT, Contact

Topic Members (click to open)

  • Elaheh Bozorgzadeh, University of California, Irvine, US, Contact
  • Francisco J. Cazorla, Barcelona Supercomputing Center, ES, Contact
  • Henk Corporaal, TU/e, NL, Contact
  • Giuseppe Desoli, STMicroelctronics, IT, Contact
  • , Contact
  • Leandro Fiorin, IBM Research, NL, Contact
  • Georgi Gaydadjiev, Chalmers University, SE, Contact
  • Nikos Hardavellas, Northwestern University, US, Contact
  • Soontae Kim, KAIST, KR, Contact
  • Benjamin C. Lee, Duke University, US, Contact
  • Hsien-Hsin Lee, Georgia Institute of Technology, US, Contact
  • Yun (eric) Liang, Peking University, CN, Contact
  • Tulika Mitra, National University of Singapore, SG, Contact
  • Andreas Moshovos, University of Toronto, CA, Contact
  • Sri Parameswaran, UNSW, AU, Contact
  • Dionisios Pnevmatikatos, Technical University of Crete, GR, Contact
  • Laura Pozzi, University of Lugano, CH, Contact
  • Antonino Tumeo, Pacific Northwest National Laboratory, US, Contact
  • Yuan Xie, Penn State University, US, Contact

Architectural and micro-architectural design techniques, memory systems, power and energy efficient architectures, multi/many-core architectures, multi-threading techniques and support for parallelism, application-specific processors and accelerators, architectural support for reliability, security, timing predictability.

D10 Temperature and Variability Aware Design and Optimization (click to open)

Topic Members (click to open)

    The topic focuses on novel methods, techniques and architectures for counteracting variability of digital circuits and systems due to manufacturing, thermal or aging effects. Themes of interest include, but are not limited to, design and run-time thermal, variability and reliability management of SoCs and multi-core platforms (both at hardware and software level), as well as modeling and optimization approaches for manufacturing and temperature variations and degradation mechanisms in emerging 3D integration and manufacturing technologies.

    D11 Reconfigurable Computing (click to open)

    Chair: Marco Platzner, University of Paderborn, DE, Contact

    Co-Chair: Ryan Kastner, University of California San Diego, US, Contact

    Topic Members (click to open)

    • Tobias Becker, Imperial College London, GB, Contact
    • Philip Brisk, University of California, Riverside, US, Contact
    • s [dot] fahmy at warwick [dot] ac [dot] uk, Contact
    • Fabrizio Ferrandi, Politecnico di Milano, IT, Contact
    • Ann Gordon-Ross, University of Florida, US, Contact
    • Yajun Ha, National University of Singapore, SG, Contact
    • Philip Leong, University of Sydney, AU, Contact
    • Enno Luebbers, Intel Open Lab Munich, DE, Contact
    • Patrick Lysaght, Xilinx, US, Contact
    • Smail Niar, University of Valenciennes, FR, Contact
    • Chao Wang, University of Science and Technology of China, Jiangsu, CN, Contact

    Statically and dynamically reconfigurable and reprogrammable systems and components: platforms and architectures, FPGAs, reconfigurable processors, design methods and tools for reconfigurable computing and communication systems.

    D12 Logic and Physical Synthesis, Timing Analysis and Verification (click to open)

    Chair: José Monteiro, INESC-ID / IST, TU Lisbon, PT, Contact

    Co-Chair: Patrick Groeneveld, Synopsys, US, Contact

    Topic Members (click to open)

    • Michel Berkelaar, Delft University of Technology, NL, Contact
    • Valentina Ciriani, University of Milano, IT, Contact
    • Azadeh Davoodi, University of Wisconsin - Madison, US, Contact
    • Elena Dubrova, Royal Institute of Technology - KTH, SE, Contact
    • Jens Lienig, Technical University of Dresden, DE, Contact
    • Igor Markov, University of Michigan, US, Contact
    • Rajeev Murgai, Synopsys, IN, Contact
    • Davide Pandini, STMicroelectronics, IT, Contact
    • Sven Peyer, IBM, DE, Contact
    • Dirk Stroobandt, Ghent University, BE, Contact
    • Tiziano Villa, University of Verona, IT, Contact
    • Alex Yakovlev, Newcastle University, GB, Contact
    • Vladimir Zolotov, IBM T.J. Watson Research Center, US, Contact

    Combinational and sequential synthesis for deep-submicron circuits; data structures for synthesis; technology mapping; performance and timing-driven synthesis; combined logic synthesis and layout design and characterization, statistical timing analysis and closure; hierarchical and non-hierarchical controller synthesis; state assignment; methods for FSM optimization, synthesis and analysis; asynchronous and mixed synchronous/asynchronous circuits; PLD and FPGA synthesis; arithmetic circuits; floorplanning; automatic place and route; interconnect- and performance-driven layout; process technology developments.

    D13 On-Chip and Off-Chip Parasitic Extraction, Model Order Reduction and Signal Integrity (click to open)

    Chair: Luca Daniel, Massachusetts Institute of Technology, US, Contact

    Co-Chair: L. Miguel Silveira, INESC ID/IST - Cadence Research Labs, PT, Contact

    Topic Members (click to open)

    • Abe Elfadel, Masdar Institute of Science and Technology, AE, Contact
    • Hai Wang, University of Electronic Science and Technology of China, CN, Contact

    Parasitic and variation-aware extraction for on-chip interconnect, and passives (including RF inductors, substrate and power grids); Macro-modeling, behavioral and reduced order modeling; Electrical characterization, modeling and optimization of off-chip interconnects, TSVs and 3D interconnects, interposer and packaging; Modeling and analysis of noise due to electromagnetic interaction of signal, power/ground and substrate; Simulation and modeling for chip-package co-design, high-speed channels and equalizers.


    Track A: Application Design (click to open)

    is devoted to the presentation and discussion of design experiences with a high degree of industrial relevance, as well as innovative design and test methodologies, and applications of specific design and test technologies. Contributions should illustrate state-of-the-art or record-breaking designs, which will provide viable solutions in tomorrow's silicon and embedded systems. In topic A7, there is the opportunity to submit short, 2-page papers that relate to industrial research and practice.

    Track Chair: Ayse Coskun, Boston University, US, Contact

    Topics

    A1 Green Computing Systems (click to open)

    Chair: Qinru Qiu, Syracuse University, US, Contact

    Co-Chair: Andreas Burg, EPFL, CH, Contact

    Topic Members (click to open)

    • Murali Annavaram, University of Southern California, US, Contact
    • Andrea Bartolini, University of Bologna, IT, Contact
    • Jungsoo Kim, Samsung, KR, Contact

    Application design experiences in industrial or academic projects with high industrial relevance or high environmental impact, targeting high performance or large-scale computing systems with a focus on energy efficiency. Target systems are massively parallel (super) computers, 2D/3D many-core systems, high performance computing clusters, data centers, cloud systems and cyber-physical systems. Topics of interest include, but are not limited to: software architectures for parallel systems and cloud computing, virtualization, energy-efficient memory, processor, or communication architectures, heterogeneous computing, resource management techniques including adaptive/learning-based methods, innovative data-center management strategies, big-data management, data centers powered by renewable energy sources, and data centers in the smart-grids.

    A2 Communication, Consumer and Multimedia Systems (click to open)

    Chair: Theocharis Theocharides, University of Cyprus, CY, Contact

    Co-Chair: Sergio Saponara, University of Pisa, IT, Contact

    Topic Members (click to open)

    • Amer Baghdadi, TELECOM Bretagne, FR, Contact
    • Christos Bouganis, Imperial College, GB, Contact
    • Marcello Coppola, STMicroelectronics, FR, Contact
    • Stefano Marsi, University of Trieste, IT, Contact
    • Guido Masera, Politecnico di Torino, IT, Contact
    • Steffen Paul, Unversity Bremen, DE, Contact
    • Ioannis Sourdis, Chalmers Univeristy of Technology, SE, Contact

    Practical design experience for communication, multimedia and consumer systems like smartphones, smart-books/tablets; examples are digital integrated circuits design of flexible baseband processing systems, Intellectual Properties for wireless communication, design challenges for software-defined/cognitive radio systems; embedded systems design in the field of audio, video and computer vision domains; Application Specific Processors (ASP), Digital Signal Processors (DSP), Multi-Processor System on Chip (MPSoC) and Network on Chip (NoC) designs for these domains.

    A3 Automotive Systems and Smart Energy Systems  (click to open)

    Chair: Bart Vermeulen, NXP Semiconductors, NL, Contact

    Co-Chair: David Boyle, Imperial College London, GB, Contact

    Topic Members (click to open)

    • Jürgen Becker, Karlsruhe Institute of Technology (KIT), DE, Contact
    • Martin Lukasiewycz, TUM CREATE, SG, Contact
    • Albrecht Mayer, Infineon, DE, Contact
    • Geoff Merrett, University of Southampton, GB, Contact
    • Wensi Wang, Tyndall National Institute, IR, Contact

    This topic covers works that describe design experiences for automotive systems, smart energy systems, energy scavenging and harvesting for embedded systems, and related applications. This includes analogue and mixed-signal integrated circuits, micro-electromechanical systems, high voltage structures, integrated sensors and transducers, RF architectures, in-vehicle networks, systems for electric vehicles, networks of systems (including car-to-car and car-to-infrastructure networks), and innovative concepts for power distribution, energy storage, and grid monitoring. Furthermore, this topic also includes design methods including models and tools, design of hardware and software components, architecture analysis and optimization, component-oriented design and system-level analysis and validation. Finally, topics of interest are also hardware and software solutions for run-time system management, including self-diagnostics and repair, energy generation, energy saving, novel energy harvesting, battery management, renewable energy subsystems, and optimization of system energy efficiency.

    A4 Ambient Intelligence and Ultra-Low Power Systems for Healthcare and Wellness (click to open)

    Chair: Srinivasan Murali, SmartCardia Sàrl, CH, Contact

    Co-Chair: Elisabetta Farella, Fondazione Bruno Kessler, IT, Contact

    Topic Members (click to open)

    • Luca Fanucci, University of Pisa, IT, Contact
    • Joaquín Recas, Complutense University of Madrid, ES, Contact
    • Francisco Rincon, EPFL, CH, Contact
    • Mohamad Sawan, Polytechnique Montreal, CA, Contact
    • Firat Yazicioglu, IMEC, BE, Contact

    Medical, healthcare, and life science applications require increasingly smarter and smaller devices enabling to easily interact among each other, with the environment and with the users in a smooth and smart way. Personal and personalized medicine and rehabilitation is leading to a significant increase in both complex lab solutions as well as a myriad of consumer-like disposable devices. This topic covers the use of ambient intelligence, wireless body sensor networks and wearable technologies for healthcare, rehabilitation and wellness. This includes but it is not limited to: technologies for ultra-low/zero power systems for personal vital signs monitoring (such as heart rate, fitness devices); mobile system for motor rehabilitation and assessment; (bio)feedback system for rehabilitation and fitness based on wearable and mobile technologies; innovative implantable miniaturized sensors and actuators, personal health devices and assistive technology; Bio-MEMS; lab-on-a-chip; power management, on-board performance optimization and networking technologies for body area networks and ambient intelligence in wellness, healthcare and fitness.

    A5 Secure Systems (click to open)

    Chair: Guido Bertoni, STMicroelectronics, IT, Contact

    Co-Chair: Tim Güneysu, Ruhr University Bochum, DE, Contact

    Topic Members (click to open)

    • Lejla Batina, Radboud University Nijmegen, NL, Contact
    • Viktor Fischer, Laboratoire Hubert Curien, FR, Contact
    • Wieland Fischer, Infineon, DE, Contact
    • Roel Maes, Intrinsic-ID, NL, Contact
    • Stefan Mangard, TU Graz, AT, Contact
    • Maire O'Neill, Queen's University Belfast, GB, Contact
    • Francesco Regazzoni, AlaRI, CH, Contact
    • Patrick Schaumont, Virginia Tech, US, Contact
    • Sebastien Tiran, LIRMM, FR, Contact
    • Ingrid Verbauwhede, KU Leuven and UCLA, BE, Contact

    Secured systems need a combination of hardware, software and embedded techniques to succeed. Indeed, the weakest link in the security chain determines the overall system security. This topic therefore invites papers on novel technologies and experiences for specific security problems as well as overall design integration methods for secure systems-on-chip and embedded systems. Topics of interest are situated at all design abstraction levels and include novel techniques and architectures for embedded cryptography; modeling, characterization, simulation and associated countermeasures for side-channel, fault and other physical attacks; random numbers generation, embedded secure processors and co-processors, trusted computing, off-chip memories and network-on-chip enciphering and integrity checking, trust establishment and attestation; implementation of security applications; hardware enabled security, including physically unclonable functions, and more.

    A6 Reliable and Reconfigurable Systems (click to open)

    Chair: Marco Domenico Santambrogio, Polimi, IT, Contact

    Co-Chair: , Contact

    Topic Members (click to open)

    • Diana Goehringer, Univ. of Bochum, DE, Contact
    • Antonio Miele, Politecnico di Milano, IT, Contact
    • Oliver Pell, Maxeler Technologies, GB, Contact
    • Christian Pilato, Columbia University, US, Contact
    • Wenjing Rao, University of Illinois at Chicago, US, Contact
    • Christian Weis, Microelectronic System Research Group, DE, Contact

    This topic covers the area of reliable and adaptive systems for practical applications. The scope of this topic includes, but not limited to, the development, optimization and practical application mechanisms to compensate for aging and temperature, development of fault-tolerant systems, redundant designs and applications, reconfigurable systems and applications, static and dynamic reconfiguration techniques, context-aware applications and self-adaptive architectures.

    A7 Industrial Experiences Brief Papers (click to open)

    Chair: Ahmed Jerraya, CEA Leti, FR, Contact

    Co-Chair: Michael Nicolaidis, TIMA, FR, Contact

    Topic Members (click to open)

    • Raphaël David, CEA LIST, FR, Contact
    • Emil Matus, Technische Universität Dresden, DE, Contact
    • Eugenio Villar, University of Cantabria, ES, Contact
    • Norbert Wehn, TU Kaiserslautern, DE, Contact
    • Shi-Jie Wen, CISCO, US, Contact

    Short or long industrial papers with a minimum size of two pages, and up to six pages, are solicited. Submissions should relate to industrial research and practice, including: commercial and market trends; future research demand; developments in design automation, embedded software, applications and test; emerging markets; technology transfer mechanisms; on-line testing and fault tolerance for industrial applications. Pure product presentations and announcements are strongly discouraged and will not be considered for publication.


    Track T: Test and Robustness (click to open)

    covering all test, design-for-test, reliability and design-for-robustness issues, at system-, chip-, circuit-, and device-level for both analog and digital electronics. Including also diagnosis, failure mode analysis, debug and post-silicon validation challenges.

    Track Chair: Cecilia Metra, University of Bologna, IT, Contact

    Topics

    T1 Defects, Faults, Variability and Reliability Analysis and Modeling (click to open)

    Chair: Robert Aitken, ARM, US, Contact

    Co-Chair: Michel RENOVELL, LIRMM, CNRS/Univ. Montpellier 2, FR, Contact

    Topic Members (click to open)

    • Bartomeu Alorda, Illes Balears University, ES, Contact
    • Sounil Biswas, NVIDIA, US, Contact
    • Bram Kruseman, NXP Semiconductors, NL, Contact
    • Kuen-Jong Lee, National Cheng Kung University, TW, Contact
    • Irith Pomeranz, Purdue University, US, Contact
    • Rosa Rodriguez, UPC, ES, Contact
    • Markus Rudack, Intel Mobile Communications GmbH, DE, Contact
    • Adit Singh, Auburn University, US, Contact
    • Mehdi Tahoori, KIT, DE, Contact

    Identification, characterization and modeling of defects, faults and degradation mechanisms; defect-based fault analysis; reliability analysis and modeling, failure mode and effect analysis (FMEA) and physics of failures; noise and uncertainty modeling; test and reliability issues in emerging technologies; modeling and mitigation of physical sources of errors such as process, voltage, temperature and aging variations; process yield modeling and enhancement; design-for-manufacturability and design-for-yield.

    T2 Test Generation, Simulation and Diagnosis (click to open)

    Chair: Bernd Becker, University of Freiburg, DE, Contact

    Co-Chair: Jacob Abraham, University of Texas at Austin, US, Contact

    Topic Members (click to open)

    • Piet Engelke, Infineon, DE, Contact
    • Grzegorz Mrugalski, Mentor Graphics Poland, PL, Contact
    • Nicola Nicolici, McMaster University, CA, Contact
    • matteo sonza reorda, politecnico di torino - DAUIN, IT, Contact
    • Arnau Virazel, LIRMM / Univ. Montpellier, FR, Contact

    Test pattern generation (TPG); fault simulation; system test; test coverage metrics and estimation; adaptive test; self-healing/self-calibration/self-adaptation; diagnosis; debug; post-silicon validation; testing at various levels of a system: embedded core, System-on-Chip, System-in-Package, 3D chips; hardware/software system test; processor based test.

    T3 Design-for-Test, Test Compression and Access (click to open)

    Chair: Paolo PRINETTO, Politecnico di Torino, IT, Contact

    Co-Chair: Magdy Abadir, Independent, US, Contact

    Topic Members (click to open)

    • Peter Harrod, ARM, GB, Contact
    • Sybille Hellebrand, University of Paderborn, DE, Contact
    • Ozgur Sinanoglu, NYU Aby Dhabi, US, Contact
    • Jerzy Tyszer, Poznan University of Technology, PL, Contact
    • Hans-Joachim Wunderlich, University of Stuttgart, DE, Contact

    Design-for-test, built-in self-test and built-in diagnosis; synthesis for testability; test resource partitioning, embedded test; test data compression; scan-based test and diagnosis; BIST for memories and regular structures, low power DFT techniques, DFT for secure systems, DFT economics; industrial test: test equipment, including ATE hardware and software, probe stations, handlers; multi-site testing; economics of test; case studies, test economics.

    T4 On-Line Test, Fault Tolerance and Robust Systems (click to open)

    Chair: Fabrizio Lombardi, Northeastern University, US, Contact

    Co-Chair: Cristiana Bolchini, Politecnico di Milano, IT, Contact

    Topic Members (click to open)

    • Jaume Abella, Barcelona Supercomputing Center, ES, Contact
    • Dan Alexandrescu, iRoC Technologies, FR, Contact
    • Lorena Anghel, TIMA, FR, Contact
    • Jie Han, University of Alberta, CA, Contact
    • Olivier Heron, CEA, FR, Contact
    • Viacheslav Izosimov, The Royal Institute of Technology (KTH), SE, Contact
    • Yiorgos Makris, The University of Texas at Dallas, US, Contact
    • Maria Michael, University of Cyprus, CY, Contact
    • Salvatore Pontarelli, University of Rome "Tor Vergata", IT, Contact
    • Mihalis Psarakis, University of Piraeus, GR, Contact
    • Pedro Reviriego, Universidad Antonio de Nebrija, ES, Contact
    • Andreas Steininger, Vienna University of Technology, AT, Contact
    • Xavier Vera, Intel, ES, Contact

    Transient fault evaluation; soft error susceptibility; on-line testing and fault tolerance for signal integrity; concurrent monitors and diagnosis; coding techniques; in-field testing and diagnosis; on-line testing; high availability systems; secure and safe circuit and system design; dependability evaluation, reliable system design; hardware/software recovery; self-repair; fault tolerance.

    DT5 Design and Test for Analog and Mixed-Signal Systems and Circuits (click to open)

    Chair: Günhan Dündar, Boğaziçi University, TR, Contact

    Co-Chair: haralampos [dot] stratigopoulos at lip6 [dot] fr, Contact

    Topic Members (click to open)

    • Florence Azais, LIRMM (CNRS - Univ. Montpellier II), FR, Contact
    • Abhijit Chatterjee, Georgia Tech, US, Contact
    • Catherine Dehollain, EPFL, CH, Contact
    • Francisco Fernandez, IMSE, CSIC and University of Sevilla, ES, Contact
    • Georges Gielen, Katholieke Universiteit Leuven, BE, Contact
    • Helmut Graeb, Technische Universitaet Muenchen, DE, Contact
    • Christoph Grimm, TU Vienna, AT, Contact
    • Lars Hedrich, University of Frankfurt, DE, Contact
    • Nuno Horta, Instituto de Telecomunicações, Instituto Superior Técnico – TU Lisbon, PT, Contact
    • Andre Ivanov, UBC, CA, Contact
    • Tom Kazmierski, University of Southampton, GB, Contact
    • Gildas Leger, IMSE-CNM-CSIC, ES, Contact
    • Dominique MORCHE, CEA-Leti, FR, Contact

    Layout and topology generation; architecture and system synthesis; formal and symbolic techniques; hardware description languages and models of computation; innovative circuit topologies and architectures; self-healing and self-calibration; test generation; fault modeling and simulation; built-in self-test; design-for-test; fault diagnosis; defect characterization and failure analysis; on-line test and fault tolerance; design-for-manufacturability and design-for-yield; test metrics and economics.


    Track E: Embedded Systems Software (click to open)

    is devoted to modelling, analysis, design and deployment of embedded software. Areas of interest include methods, tools, methodologies and development environments. Emphasis will also be on modelbased design and verification, embedded software platforms, software compilation and integration, real-time systems, cyber-physical systems, networked and dependable systems.

    Track Chair: Lothar Thiele, ETH Zurich, CH, Contact

    Topics

    E1 Real-time, Networked, and Dependable Systems (click to open)

    Chair: Iain Bate, University of York, GB, Contact

    Co-Chair: Rodolfo Pellizzoni, University of Waterloo, CA, Contact

    Topic Members (click to open)

    • Benny Akesson, CISTER-ISEP Research Centre, Polytechnic Institute of Porto, PT, Contact
    • Liliana Cucu, INRIA, FR, Contact
    • Dionisio de Niz, Carnegie Mellon University, US, Contact
    • Arvind Easwaran, Nanyang Technical University, SG, Contact
    • Raimund Kirner, University of Hertfortshire, GB, Contact
    • Kai Lampka, Uppsala University, SE, Contact
    • Giuseppe Lipari, Scuola Superiore Sant'Anna, IT, Contact
    • Dorin Maxim, ISEP, PT, Contact
    • Florian Pölzlbauer, Virtual Vehicle, AT, Contact
    • Sasikumar Punnekkat, Malardalen University, SE, Contact
    • Binoy Ravindran, Virginia Tech, US, Contact
    • Jan Reineke, Informatik, Universität des Saarlandes, DE, Contact
    • Sebastian Stiller, TU Berlin, DE, Contact
    • Patrick Meumeu Yomsi, ISEP, PT, Contact

    Real-time programming languages and software; formal models for real-time systems; software performance analysis; worst case execution time analysis; scheduling and software timing estimation; real-time system optimization; tools and design methods for real-time, networked and dependable systems; adaptive real-time systems; dependable systems including safety and criticality; software for safety critical systems; network control and QoS for embedded applications; software for sensor networks and networked applications

    E2 Compilers for Embedded Systems (click to open)

    Chair: Alain Darte, ENS Lyon - INRIA, FR, Contact

    Co-Chair: Rodric Rabbah, IBM Research, US, Contact

    Topic Members (click to open)

    • Heiko Falk, Hamburg University of Technology (TUHH), DE, Contact
    • Sebastian Hack, University of Saarland, DE, Contact
    • Frank Hannig, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE, Contact
    • Claire Maiza, IMAG, FR, Contact
    • Jingling Xue, University of New South Wales, AU, Contact

    Compilers for embedded multi-core, heterogeneous, GPU, reconfigurable, or FPGA platforms; compiler-related tools for design space exploration, for iterative compilation, to complement HLS tools; just-in-time compilation and libraries for embedded and mobile devices; compiler support for enhanced debugging, profiling, and traceability; code analysis, optimization, and generation for different metrics (e.g., power, memory lifetime, WCET, etc.); compilation of domain specific or streaming languages for embedded systems; compilation tools for embedded systems as cloud services; certified compilers.

    E3 Model-based Design and Verification for Embedded Systems (click to open)

    Chair: Saddek Bensalem, Université Joseph Fourier, FR, Contact

    Co-Chair: Linh Thi Xuan Phan, University of Pennsylvania, US, Contact

    Topic Members (click to open)

    • Borzoo Bonakdarpour, University of Waterloo, CA, Contact
    • Petru Eles, Linköping University, SE, Contact
    • Alain Girault, INRIA, FR, Contact
    • Oleg Sokolsky, University of Pennsylvania, US, Contact
    • Wang Yi, Uppsala University, SE, Contact

    Verification techniques for embedded systems ranging from simulation, testing, model-checking, SAT and SMT-based reasoning, compositional analysis and analytical methods. Modeling, analysis and optimization of non-functional and performance aspects such as timing, memory usage, QoS and reliability. Model-based design of software architectures and deployment. Theories, languages and tools supporting model-based design flows covering software, control and physical components.

    E4 Embedded Software Architectures (click to open)

    Chair: Marc Geilen, TU Eindhoven, NL, Contact

    Co-Chair: , Contact

    Topic Members (click to open)

    • Oliver Bringmann, FZI / University of Tuebingen, DE, Contact
    • Gero Dittmann, IBM Research, CH, Contact
    • Akash Kumar, Electrical and Computer Engineering, National University of Singapore, SG, Contact
    • Orlando Moreira, Ericsson, NL, Contact
    • Alex Orailoglu, UC San Diego, US, Contact
    • Tanguy Risset, Insa-Lyon, FR, Contact
    • Gunar Schirner, Norhteastern University, US, Contact

    Software architectures for MPSoC, multi/many-core and (GP)GPU-based systems; Programming paradigms and languages for embedded MPSoCs, multi/many-core and (GP)GPU-based systems; Virtualization and middleware for embedded systems, including resource-awareness, reconfiguration, safety and security aspects; Software support for reconfigurable components and accelerators; Software architectures for low power and temperature awareness

    E5 Cyber-Physical Systems (click to open)

    Chair: Rolf Ernst, TU Braunschweig, DE, Contact

    Co-Chair: Paul Pop, Technical University of Denmark, DK, Contact

    Topic Members (click to open)

    • Tarek Abdelzaher, University of Illinois at Urbana Champaign, US, Contact
    • Karl-Erik Arzen, Lund University, SE, Contact
    • Jean-Dominique Decotignie, EPFL, CH, Contact

    Modeling, design, architecture, optimization, and analysis of Cyber-Physical Systems (CPS); Modeling techniques for large-scale cyber physical systems design and analysis; Verification and validation in CPS; Safety and cybersecurity in CPS systems; Internet of things and CPS: modeling, analysis, and design; Software-intensive CPS; Data-mining and CPS; Autonomous and semi-autonomous large-scale CPS and related issues; Socio-technical systems (ex. empowered consumer and organizational behavior in smart grids) and CPS; Cognitive control for CPS; Modeling and analysis of networked control, switched control, and distributed control systems in CPS; control/architecture co-design in CPS; architecture-aware controller synthesis; Case studies in CPS ranging from automotive systems, and avionics, to smart buildings and smart grids