Each year the Design, Automation and Test in Europe Conference presents awards to the authors of the best papers. The selection is performed by an award committee, based on the results of the reviewing process and the quality of the final paper.
PHASENOC: TDM SCHEDULING AT THE VIRTUAL-CHANNEL LEVEL FOR EFFICIENT NETWORK TRAFFIC ISOLATION
Anastasios Psarras1, Ioannis Seitanidis1, Chrysostomos Nicopoulos2 and Giorgos Dimitrakopoulos1
1Democritus University of Thrace, GR; 2University of Cyprus, CY
HARDWARE TROJAN DETECTION FOR GATE-LEVEL ICS USING SIGNAL CORRELATION BASED CLUSTERING
Burcin Cakir and Sharad Malik, Princeton University, US
DIGITAL CIRCUITS RELIABILITY WITH IN-SITU MONITORS IN 28NM FULLY DEPLETED SOI
Marine Saliva1, Florian Cacho1, Vincent Huard1, Xavier Federspiel1, Damien Angot1, Ahmed Benhassain1, Alain Bravaix2 and Lorena Anghel3
1STMicroelectronics, FR; 2IM2NP-ISEN, FR; 3TIMA, FR
ASYMMETRIC UNDERLAPPED FINFET BASED ROBUST SRAM
DESIGN AT 7NM NODE
Arun Goud Akkala, Rangharajan Venkatesan, Anand Raghunathan, Kaushik Roy
Purdue University
FAST EYE DIAGRAM ANALYSIS FOR HIGH-SPEED CMOS CIRCUITS
Seyed Nematollah Ahmadyan, Shobha Vasudevan
University of Illinois at Urbana-Champaign
Eli Chiprout, Chenjie Gu, Suriyaprakash Natarajan
Intel
A track
WORKLOAD UNCERTAINTY CHARACTERIZATION AND ADAPTIVE FREQUENCY SCALING
FOR ENERGY MINIMIZATION OF EMBEDDED SYSTEMS
Anup Das, Akash Kumar, Bharadwaj Veeravalli, Rishad Shafik, Geoff Merrett, Bashir Al- Hashimi
University of Southhampton, National University of Singapore
AN ULTRA-LOW POWER DUAL-MODE ECG MONITOR FOR HEALTHCARE AND WELLNESS
Daniele Bortolotti, Mauro Mangia,Andrea Bartolini, Riccardo Rovatti,
Gianluca Setti, Luca Benini
University of Bologna
University of Ferrara, ETH Zurich
REDUCING TRACE SIZE IN MULTIMEDIA APPLICATIONS ENDURANCE TESTS
Serge Vladimir Emteu Tchagou, Alexandre Termier, Jean-François Méhaut, Brice Videau,
Miguel Santana, René Quiniou
University of Grenoble Alpes, STMicroelectronics, University of Rennes, INRIA Rennes
T track
GPU-ACCELERATED SMALL DELAY FAULT SIMULATION
Eric Schneider, Stefan Holst, Michael Kochte, Xiaoqing Wen, Hans-Joachim Wunderlich
University of Stuttgart, Kyushu Institute of Technology
Category “New Directions in Logic and System Design”
Zhenyu Sun, Ph.D.
High-Performance And Low-Power Magnetic Material Memory Based Cache Design
Category “New Directions in Physical Design, Design for Manufacturing and CAD for Analogue Circuits and MEMS”
Bei Yu, Ph.D.
Design for Manufacturing with Advanced Lithography
Category “New Directions in Logic and System Test”
Brandon Robert Noia, Ph.D.
Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs