5.2 Hardware Trojan and Active Implementation Attacks
Date: Wednesday 11 March 2015
Time: 08:30 - 10:00
Location / Room: Belle Etoile
Chair:
Paolo Maistri, TIMA, FR
Co-Chair:
Viktor Fischer, Hubert Curien Laboratory, FR
This session proposes novel techniques to detect hardware Trojans inserted at gate level and presents improvements and novel targets for fault attacks.
| Time | Label | Presentation Title Authors |
|---|---|---|
| 08:30 | 5.2.1 | IMPROVED PRACTICAL DIFFERENTIAL FAULT ANALYSIS OF GRAIN-128 Speakers: Prakash Dey1, Abhishek Chakraborty2, Avishek Adhikari1 and Debdeep Mukhopadhyay2 1Department of Pure Mathematics, University of Calcutta, Kolkata-700019, IN; 2Department of Computer Science and Engineering, Indian Institute of Technology Kharagpur, Kharagpur-721302, IN Abstract Differential Fault Attacks (DFA) on stream ciphers have been an active field of research. However, their practical realizations have not been reported in the public literature. Hence, the assumptions on the fault models made in the context of DFA for stream ciphers have not been studied. Furthermore, there have been few efforts reported on the popular stream cipher candidate, Grain-128. We consider a simple low-cost fault injection set-up, using clock glitches and show that in stream ciphers the critical path of the circuit affects few bit positions (the feedback bit for the Shift Registers in the stream ciphers). Thus the fault is often localized to single bit position, and because of the absence of required faulty ciphers makes existing theoretical DFAs invalid. In order to create multiple instance of faults, we use clock glitches to induce the fault, and then use the shifting property of the internal registers of Grain to create multiple instances of contiguously located faults. In parallel, we also develop a more relaxed DFA for Grain-128, to show that when the fault is k neighbourhood bits, $k in {1,..,5}$, the attack is successful to retrieve the key without knowing the locations or exact number of bits flipped by the internal fault. We also devise a technique for rejecting the bad faults with high probabilities, i.e., when the faults are not in the contiguous location as required in the attack. Combining the above attacks we demonstrate using a simple set-up via clock glitches that such faults can be practically obtained and analysed using the proposed attack algorithm to retrieve the key. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:00 | 5.2.2 | A SCORE-BASED CLASSIFICATION METHOD FOR IDENTIFYING HARDWARE-TROJANS AT GATE-LEVEL NETLISTS Speakers: Masaru Oya, Youhua Shi, Masao Yanagisawa and Nozomu Togawa, Waseda University, JP Abstract Recently, digital ICs are often designed by outside vendors to reduce design costs in semiconductor industry, which may introduce severe risks that malicious attackers implement Hardware Trojans (HTs) on them. Since IC design phase generates only a single design result, an RT-level or gate-level netlist for example, we cannot assume an HT-free netlist or a Golden netlist and then it is too difficult to identify whether a generated netlist is HT-free or HT-inserted. In this paper, we propose a score-based classification method for identifying HT-free or HT-inserted gate-level netlists without using a Golden netlist. Our proposed method does not directly detect HTs themselves in a gate-level netlist but a net included in HTs, which is called Trojan net, instead. Firstly, we observe Trojan nets from several HT-inserted benchmarks and extract several their features. Secondly, we give it scores to extracted Trojan net features and sum up them for each net in benchmarks. Then we can find out a it score threshold to classify HT-free and HT-inserted netlists. Based on these scores, we can successfully classify HT-free and HT-inserted netlists in all the Trust-HUB gate-level benchmarks. Experimental results demonstrate that our method successfully identify all the HT-inserted gate-level benchmarks to be HT-inserted and all the HT-free gate-level benchmarks to be HT-free in approximately three hours for each benchmark. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 09:30 | 5.2.3 | (Best Paper Award Candidate) HARDWARE TROJAN DETECTION FOR GATE-LEVEL ICS USING SIGNAL CORRELATION BASED CLUSTERING Speakers: Burcin Cakir and Sharad Malik, Princeton University, US Abstract Malicious tampering of the internal circuits of ICs can lead to detrimental results. Insertion of Trojan circuits may change system behavior, cause chip failure or send information to a third party. Trojans are hidden cleverly by the adversary to evade detection using typical pre-silicon verification and post-manufacturing testing. Therefore, the validation of chips to detect these has emerged as an important problem, particularly for safety-critical applications. This paper presents an information-theoretic approach for Trojan detection. It estimates the statistical correlation between the signals in a design, and explores how this estimation can be used in a clustering algorithm to detect the Trojan logic. The gate level circuit is modeled as a weighted graph. The edge weights are determined using correlations between the signal transitions at the inputs and outputs of a gate based on simulation data. These weights are used to compute a distance metric in a density-based clustering algorithm. This approach exploits the fact that Trojans have a stealthy nature. The nodes which are nearly unused and hence, have weak correlation with the rest of the circuit, are detected as outliers by this clustering method and flagged as suspicious. Compared with the other algorithms, our tool does not require extensive logic analysis. We neither need the circuit to be brought to the triggering state, nor the effect of the Trojan payload to be propagated and observed at the output. Instead we leverage already available simulation data in this information-theoretic approach. We conducted experiments on the TrustHub benchmarks to validate the practical efficacy of this approach. The results show that our tool can detect Trojan logic with up to 100% coverage with low false positive rates. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | IP2-5, 46 | FAULT-BASED ATTACKS ON THE BEL-T BLOCK CIPHER FAMILY Speakers: Philipp Jovanovic and Ilia Polian, University of Passau, DE Abstract We present the first fault-based attack on the Bel-T block cipher family which has been adopted recently as a national standard of the Republic of Belarus. Our attack successfully recovers the secret key of the 128-bit, 192-bit and 256-bit versions of Bel-T using 4, 7 and 10 fault injections, respectively. We also show the results from our comprehensive simulation-based experiments. Download Paper (PDF; Only available from the DATE venue WiFi) |
| 10:00 | End of session Coffee Break in Exhibition Area Coffee Break in Exhibition AreaOn all conference days (Tuesday to Thursday), coffee and tea will be served during the coffee breaks at the below-mentioned times in the exhibition area. Lunch BreakOn Tuesday and Wednesday, lunch boxes will be served in front of the session room Salle Oisans and in the exhibition area for fully registered delegates (a voucher will be given upon registration on-site). On Thursday, lunch will be served in Room Les Ecrins (for fully registered conference delegates only). Tuesday, March 10, 2015Coffee Break 10:30 - 11:30 Lunch Break 13:00 - 14:30; Keynote session from 13:20 - 14:20 (Room Oisans) sponsored by Mentor Graphics Coffee Break 16:00 - 17:00 Wednesday, March 11, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:30, Keynote lectures from 12:50 - 14:20 (Room Oisans) Coffee Break 16:00 - 17:00 Thursday, March 12, 2015Coffee Break 10:00 - 11:00 Lunch Break 12:30 - 14:00, Keynote lecture from 13:20 - 13:50 Coffee Break 15:30 - 16:00 |
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