W5 3D Integration: Applications, Technology, Architecture, Design, Automation, and Test

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Chair: Paul Franzon, North Carolina State University, US


08:15  Welcome Address

Saqib Khursheed, University of Liverpool, UK


08:20 Keynote Presentation: 3D Technology – Key Enabler for 3D Heterogeneous Integration

Jürgen Wolf, IZM Fraunhofer, DE.



3D integration is a key technology for microelectronics to meet the growing demands regarding more functionality, increase in performance, miniaturization and cost reduction and becomes important for application areas e.g. cyber physical systems, internet of things, ambient assisted living (AAL), information & communication, security and health. Interposers with Through Silicon Vias (TSVs) are becoming a very important element and a key enabler for the realization of 3D Systems-in-Packages (SiPs) whose main advantages are the decoupling of front end / back end processing for the implementation of TSVs and redistribution layers to integrate multiple devices into a system in package (WL-SiP). Specific applications result in technical approaches ranging from high density TSV integration, high density RDL for digital applications to interposers for RF applications as well as MEMS and sensor integration and optical interconnects. The presentation will highlight results and technical achievements for 3D integration using TSV interposer and addresses also the broad spectrum of topics from design, technology and reliability related to 3D systems.



M. Jürgen Wolf studied electrical engineering and joined Fraunhofer Institute for Reliability and Microintegration (IZM) in 1994 working in the field of wafer level packaging and system in package (SiP). Since 2011 he is head of department Wafer Level System Integration and also responsible for the management of “ASSID - All Silicon System Integration Dresden”. He is also involved in a number of research projects on national, European and international level. Wolf is a European representative in the technical working group Assembly & Packaging of ITRS, a board member of EURIPIDES, JISSO and a member of IEEE/SMTA. Furthermore, he is a representative of the Fraunhofer Cluster 3D Integration.

09:00  Special Session: Reliability and Thermal issues in 3D ICs


09:00  Overview of 3D-Reliability Research in Imec

Kristof Croes – IMEC, BE


09:20  Advanced Failure Analysis Techniques for 3D Packages

Frank Altmann - Fraunhofer IWM Halle, DE


09:40  Research Directions on Thermal Impact of 3D Assembly

Haykel Ben Jaama- CEA-LETI, FR


10:00  SESSION 2: Coffee Break & Posters


10:30  SESSION 3: Invited Talk and Panel


10:30  Invited Talk: Heterogeneous Sensor Integration; Increased Technology Readiness Level

Maaike Visser - SINTEF, Norway


11:00  Panel Session: Are Slow Standardization and CAD-Tool Development Hindering the Progress of 3D IC Design and Integration?


Moderator: Françoise Von Trapp – “Queen of 3D”, 3DInCites, US


Panelists:                       Brandon Wang – Cadence Design Systems, US

Juergen Schloeffel – Mentor Graphics, DE

Makoto Nagata  – Kobe University, JP

Mustafa Badaroglu – Qualcomm Technologies, BE




13:00 SESSION 4: Technology and Design Challenges for 3D ICs

Chair: Thomas Thärigen, Cascade Microtec GmbH, DE


13:00 Integration of Through -Silicon Vias in a High Performance BiCMOS Technology for RF -Grounding and 3D -Integration

M. Wietstruck1, M. Kaynak1, S. Marschmeyer1, K. Zoschke2, and B. Tillack1,3

1 IHP,DE ;  2 Fraunhofer IZM, DE ; 3 Technische Universität Berlin, DE


13:18 2.5D & 3D Technologies require Innovative Lithography Solutions

Klaus Ruhmer, Philippe Cochet,Roger McCleary

Rudolph Technologies, US


13:36 3D Wirebondless IGBT Module for High Power Applications

Z. Y. Gao1, Y. X. Ren1, Y.C. Lee2, H.L. Yiu2, X.Q. Shi1

1 Hong Kong Applied Science & Technology Research Institute (ASTRI), HK; 2Hong Kong Science & Technology Parks Corporation (HKSTP), HK


13:54 Towards Trustworthy NoC-Based 3D-MPSoCs

Johanna Sepúlveda1,2, Guy Gogniat2, Marius Strum1

1 University of São Paulo, BR;  2 LAB-STICC, Lorient, FR


14:12 A TSV-Property-aware Synthesis Method for Application Specific 3D-NoCs

Felix Miller, Thomas Wild, Andreas Herkersdorf, Vladimir Todorov, Daniel Mueller-Gritschneder, Ulf Schlichtmann

Technische Universität, München, DE


14:30   SESSION 5: Coffee Break & Posters


15:00   SESSION 6: Test and Thermal Challenges for 3D ICs

Chair: Basel Halak, U of Southampton, UK


15:00   Design, Test Generation, Processing, and Pre- and Post-Bond Measurement Results of a 3D-DfT Demonstrator Chip Stack

Erik Jan Marinissen1, Bart De Wachter1, Stephen O’Loughlin1, Sergej Deutsch2, Christos Papameletis2, Tobias Burgherr2

1IMEC, BE ; 2Cadence Design Systems, DE


15:18    Power and DFT Aware Partitioning for 3D-SOCs

Amit Kumar and Sudhakar M. Reddy

University of Iowa, US


15:36   System Level Thermal Modelling for 3D IC: A Memory-on-Logic 3D Test Case Study

Cristiano Santos 1,3, Pascal Vivet1, Denis Dutoit1, Philippe Garrault2, Nicolas Peltier2, Ricardo Reis3



15:54   Thermal Power Plane enabling Dual-Side Electrical Interconnects supporting High-Performance Chip Stacking

Thomas Brunschwiler1, Stefano Oggioni2, Timo Tick1, Gerd Schlottig1, Hubert Harrer3

1IBM Research, Zurich, CH; 2IBM ISC, Milan, IT; 3IBM STG, Böblingen, DE


16:12  Thermal Coupling in TSV-Based 3-D Integrated Circuits

Ioannis Savidis1 and Eby G. Friedman2

1Drexel University, US;  2University of Rochester, US


16:30  CLOSE 


A Novel Low-Power TSV Interconnection Scheme Based On Adiabatic Energy-Recovery Logic

Khaled Salah

Mentor Graphics, Cairo, Egypt


3D IC Test through Power Line Methodology

Alberto Pagani, Alessandro Motta

STMicroelectronics – SPA FMTR&D (Sense, Power & Automotive Front-end Manufacturing & Technology R&D)


2.5D Test Cost Optimization using 3D-COSTAR

Mottaqiallah Taouil1, Said Hamdioui1, Erik Jan Marinissen2 and Sudipta Bhawmik3

1Delft University of Technology, NL, 2IMEC, BE,  3Qualcomm, US


Test Pattern Retargeting in 3D SICs Using an IEEE P1687 based 3DFT architecture

Yassine Fkih1,2, Pascal Vivet1, Bruno Rouzeyre2, Marie-Lise Flottes2, Giorgio Di Natale2, Juergen Schloeffel3

1CEA-Leti, MINATEC Campus, FR, 2LIRMM, Univ Montpellier II/CNRS, FR, 3Mentor Graphics, DE


Impact Analysis of Through-Silicon-Via Variation on Performance and Energy Consumption of 3D Networks-on-Chip Architectures

Michael Opoku Agyeman, Ali Ahmadinia

School of Engineering and Built Environment Glasgow Caledonian University, Glasgow, UK


Processing and Microstructure of Solid-Liquid Interdiffusion Interconnects for 3D Integration

Iuliana Panchenko1, Juergen Grafe1, Maik Mueller2, Klaus-Juergen Wolter2, M. Juergen Wolf1, Klaus-Dieter Lang1

1Fraunhofer IZM ASSID, Moritzburg, Germany, 2Electronics Packaging Laboratory, TU Dresden, Dresden, Germany



M. Juergen Wolf , K.-D. Lang

Fraunhofer IZM ASSID, Berlin, Dresden, Germany