Date: Wednesday 26 March 2014
Time: 12:00 - 14:00
Location / Room: University Booth, Booth 3, Exhibition Area

Label	Presentation Title Authors
UB06.01	SOC VERIFICATION: AUTOMATED FUNCTIONAL VERIFICATION OF SYSTEMS-ON-CHIP Authors: Zdenek Prikryl, Marcela Simkova and Karel Masarik, Faculty of Information Technology, Brno University of Technology, CZ Abstract An increase of the complexity of systems-on-chip (SoC) induces an increase of the complexity of their verification as well. The reason is that we must verify not only the functions of separate logic blocks, but we need to check their interconnections, timing and functional collaboration as well. Therefore, there is still a great demand for verification tools, which are time-effective, fast and as automated as possible. Exactly these issues we target in our solution. You are welcome to see the live demonstration at our booth! More information ...
UB06.02	HIPACC: AUTOMATIC GPU CODE GENERATION FOR ANDROID Authors: Oliver Reiche1, Richard Membarth2, Frank Hannig1 and Jürgen Teich1 1University of Erlangen-Nuremberg, DE; 2Saarland University, DE Abstract We present the Heterogeneous Image Processing Acceleration (HIPAcc) framework. It allows programmers to develop image preprocessing applications while providing high productivity, flexibility, and portability as well as competitive performance. The same algorithm description serves as basis for targeting different GPU accelerators and low-level languages. Hereby, imaging algorithms can be expressed in a compact and productive way by using a domain-specific language (DSL) that is embedded into C ++ code. Using the HIPAcc source-to-source compiler, DSL code is compiled to CUDA, OpenCL, C/C ++, or even Renderscript code, which targets heterogeneous architectures on recent MPSoCs running Android. Programming those MPSoCs can be challenging, in particular when targeting different architectures (CPU/GPU/DSP). HIPAcc lifts this burden from programmers by automatically applying source code transformations based on domain knowledge and a built-in architecture model. This demonstration shows the seamless integration of HIPAcc into the Android Developer Tools and provides a live comparison of generated code to functional identical handwritten naive implementations of image filters on recent MPSoCs running Android. More information ...
UB06.03	CUCUMBER-VERILOG: BEHAVIOR DRIVEN DEVELOPMENT FOR CIRCUIT DESIGN AND VERIFICATION Authors: Melanie Diepenbeck, Mathias Soeken, Ulrich Kühne and Rolf Drechsler, University of Bremen, DE Abstract When designing hardware one usually applies a top-down approach in which starting from a natural language specification a design is implemented and afterwards tested and verified for correctness. In contrast, software development is pushed towards agile techniques such as Test Driven Development (TDD), where tests play a central role in driving the implementation. Behavior Driven Development (BDD) extends TDD by using natural language style scenarios to describe the tests. Essentially, in both techniques testing and implementation is interleaved: first, test cases are written, and secondly, the implementation is extended to satisfy them. Since nowadays 70% of the the effort to design hardware systems is spent on verification, test and verification should receive more attention and be applied as soon as possible. We present a BDD tool tailored for the Verilog hardware description language which enables a new design flow for hardware design, test, and verification. BDD acceptence tests are readily given by means of the natural language specification. Assigning test code to their sentences yields a testbench which serves as a starting point for the implementation. In the same time, the natural language scenarios form a test documentation that is easily accessable also to non-experts. Furthermore, our tool allows for the generalization of test cases to properties suitable for formal verification. As properties are typically more difficult to formalize than test cases, our approach facilitates the access to formal verification. In our demonstration, we will show how to implement hardware designs using our BDD tool and how properties are generalized from test cases which can then can be verified by a model checker automatically. More information ...
UB06.04	COMPILER FOR MAPPING STREAM PROCESSING APPLICATIONS ONTO REAL-TIME HETEROGENEOUS MULTIPROCESSOR SYSTEMS Authors: Stefan Geuns, Berend Dekens, Philip Wilmanns, Joost Hausmans, Guus Kuiper and Marco Bekooij, University of Twente, NL Abstract Heterogeneous multiprocessors system are employed for power-efficiency reasons in wearable software defined radios. These systems are hardware cost-effective and deliver a superior performance compared to their homogeneous counterparts. However these systems are notoriously hard to program without tool support, which makes it is desirable that programming is simplified with the help of an optimizing multiprocessor compiler for stream processing applications. This demonstration shows our multiprocessor compiler for mapping real-time stream processing applications onto our real-time heterogeneous multi-core system. The applications are described as sequential programs and are compiled into parallel task graphs. Buffer capacities are computed using dataflow analysis techniques given the real-time constraints of the application. Our multi-core system contains 16 MicroBlaze processor cores as well as two hardware accelerators and is prototyped on a Xilinx Virtex-6 FPGA. A connection-less communication ring is used for inter-processor communication. Our system is equipped with an analog RF front-end, which enables us to demonstrate PAL-video reception and decoding. More information ...
UB06.05	S4ECOB APU: ENERGY-EFFICIENT HIGH-PERFORMANCE ACOUSTIC PROCESSING UNIT Authors: Wolfram Kattanek1, Sebastian Uziel1, Thomas Elste1, Stephan Gerlach2, Danilo Hollosi2 and Stefan Goetze2 1Institut für Mikroelektronik- und Mechatronik-Systeme gemeinnützige GmbH, DE; 2Fraunhofer Institute for Digital Media Technology, IDMT Project Group Hearing, Speech and Audio Technology, DE Abstract An embedded 24-channel acoustic processing system consisting of an FPGA based front-end and a multi-core microcontroller subsystem is presented here. It is specifically designed for a smart building solution estimating the occupancy level of rooms and areas solely based on acoustic features and source localization. The overall goal is to use this occupancy estimate to lower the energy consumption of large buildings. An overview of the hardware and software concept as well as a brief description of the acoustic occupancy level estimation is given. The APU was developed as part of the EU FP7 project - Sounds for Energy Control of Buildings (S4ECoB). More information ...
UB06.06	SCOPE: TIME-DECOUPLED PARALLEL SYSTEMC SIMULATION Authors: Jan Weinstock1, Christoph Schumacher2, Rainer Leupers2, Gerd Ascheid2 and Laura Tosoratto3 1RWTH Aachen University, DE; 2Institute for Communication Technologies and Embedded Systems, RWTH Aachen University, DE; 3Istituto Nazionale di Fisica Nucleare - Sezione di Roma, IT Abstract With increasing system size and complexity, designers of embedded systems face the challenge of efficiently simulating these systems in order to enable target specific software development and design space exploration as early as possible. Today's multicore workstations offer enormous computational power, but traditional simulation engines like the OSCI SystemC kernel only operate on a single thread, thereby leaving a lot of computational potential unused. Most modern embedded system designs include multiple processors. This work proposes SCope, a SystemC kernel that aims at exploiting the inherent parallelism of such systems by simulating the processors on different threads. A lookahead mechanism is employed to reduce the required synchronization between the simulation threads, thereby further increasing simulation speed. The virtual prototype of the European FP7 project EURETILE system simulator is used as demonstrator for the proposed work, showing a speedup of 4x on a four core host system compared to sequential simulation. The demo will visualize the simulation of the EURETILE system using an OpenGL based graphical user interface. The simulator will be presented as a regular sequential version based on OSCI SystemC, and as a parallel version based on the new SCope parallel SystemC kernel. More information ...
UB06.07	COMPSOC: VIRTUAL EXECUTION PLATFORMS FOR MIXED TIME-CRITICALITY APPLICATIONS Author: Kees Goossens, TU Eindhoven, NL Abstract System-on-Chip (SOC) design gets increasingly complex, as a growing number of applications are inte- grated in such systems. These applications have mixed time-criticality, i.e., some have firm-, some soft-, and others non-real-time requirements. Executing such a mix of applications on a SOC poses several challenges. First, to reduce cost, platform resources, e.g., processors, interconnect, memories, are shared between applications. However, sharing causes interference between applications, making their behaviors inter- dependent. This results in two problems for SOC design and verification: 1) accurate system-level simulation and several approaches to formal verification are infeasible, because of the explosion in the number of possible combinations of applications, inputs, and resource states and 2) verification becomes a circular process that must be repeated if an application is added, removed, or modified, making integration and verification dominant parts of SOC development, in terms of time and money. The CompSOC platform addresses these problems by executing each application on an independent virtual execution platform (VEP). The VEPs are composable, i.e., cannot affect each other's behaviors. In the temporal domain an applications actual execution never varies by even a single clock cycle. Similarly, the energy and power behaviors of applications are also composable. As a result, applications can be designed, developed, verified, and executed in isolation. The VEPs are also predictable, meaning that all interference is bounded. This makes them virtualized also in terms of performance bounds, which enables firm real-time applications to be verified using formal performance analysis frameworks. The CompSOC platform uses the CoMiK microkernel to implement virtual processors on each processor time through temporal partitioning. Each application can use its own operating system (e.g. Compose, μcOS-III) and model of computation (e.g. CSDF, KPN, TT) in its VEP, to suit its level of time criticality. As more applications are integrated on a single SOC, the need arises for more dynamic behaviour. The system should be able to start, modify and stop applications at run time without affecting running appli- cations. For this purpose the CompSOC platform has been extended with a predictable and composable resource management framework. It manages application bundles that contain 1) an application in the form of executables (ELFs on multiple processors), and also 2) the specifications of the (one or more) particular VEPs that the application executes in, consisting of virtual processors, NOC connections, virtualised mem- ories, etc. At run time, the resource management framework can dynamically load and start application bundles by creating a VEP and then loading, booting, and executing an application within it. VEPs can also be modified, stopped, and deleted at run time. Our University Booth will present virtual-execution-platform and application-bundle concepts using an interactive demonstrator. It will show that the CompSOC has been extended with dynamic functionality, without sacrificing its key strengths: composability and predictability. We will demonstrate this through the use of the resource management framework and application bundles, showing that we can create, modify and delete virtual execution platforms running a mixed time-criticality application dynamically at run-time. More information ...
UB06.08	TTOOL/DIPLODOCUSDF: A UML ENVIRONMENT FOR HARDWARE/SOFTWARE CO-DESIGN OF DATA-DOMINATED SYSTEMS-ON-CHIP Authors: Andrea Enrici, Ludovic Apvrille and Renaud Pacalet, Telecom ParisTech, FR Abstract The development of new Systems on Chip commonly relies on previous products for whom, due to factors such as system complexities, time and cost constraints, little design space exploration can be performed. Hardware and software are typically composed as if they were separate components, whereas their interactions yield more than the sum of the two parts. In the scope of the demonstration, we present our enhanced version of TTool/DiplodocusDF, a UML model-driven engineering tool and methodology for the design of heterogeneous data processing systems. Our contributions enrich the modeling and design space exploration capabilities of TTool/DiplodocusDF to target complex transfer schemes and control information exchange at different abstraction levels. Our ameliorated methodology is applied to two signal processing applications, showing the analysis of novel interactions between typically conflicting aspects such as computations vs communications and dataflows vs controlflows. More information ...
UB06.09	PIGGY'S WEAVER: A DEMONSTRATION FOR FOCUSING ON SEPARATION OF DEBUGGING CONCERNS BASED ON DYNAMIC PROGRAM REWRITING TOOL: PIGGY'S WEAVER Authors: Ikuta Tanigawa1, Nobuhiko Ogura2, Midori Sugaya3 and Harumi Watanabe1 1Tokai University, JP; 2Tokyo City University, JP; 3Shibaura Institute of Technology, JP Abstract Dynamic program rewriting is needed to continuous work and reduces costs of maintenance. We propose a dynamic rewriting tool "Piggy's Weaver" for C# program. The tool attaches and detaches pieces of code to program at any points on each concern. Especially these attachments are focused on debugging concern. In the demonstration, we will apply the tool to a cloud and embedded system "Piggy Net" which is a cooperating charity pot with SNS and was awarded 2nd prize on D2C2012 by Microsoft Japan. More information ...
UB06.10	UNISON: ASSEMBLY CODE GENERATION USING CONSTRAINT PROGRAMMING Authors: Roberto Castañeda Lozano1, Gabriel Hjort Blindell2, Mats Carlsson1 and Christian Schulte2 1Swedish Institute of Computer Science, SE; 2KTH Royal Institute of Technology, SE Abstract We demonstrate Unison - a simple, flexible and potentially optimal code generator that solves interdependent code generation tasks together using constraint programming as a modern combinatorial optimization method. We show how Unison takes into account the task interdependencies and their combinatorial nature to improve the speed of the code generated by LLVM (a state-of-the-art compiler) for Hexagon (a digital signal processor ubiquitous in modern mobile platforms). More information ...
14:00	End of session
16:00	Coffee Break in Exhibition Area On Tuesday-Thursday the coffee and lunch breaks will be located in the Exhibition Area (Terrace Level).