Date: Wednesday 26 March 2014
Time: 10:00 - 12:00
Location / Room: University Booth, Booth 3, Exhibition Area

Label	Presentation Title Authors
UB05.01	DESIGN SPACE EXPLORATION FOR A LANE-KEEPING-SUPPORT CASE STUDY Authors: Raphael Weber1, Eike Thaden1, Stefan Henkler2, Jens Höfflinger3 and Steffen Prochnow4 1OFFIS, DE; 2OFFIS, Germany, DE; 3Robert Bosch GmbH, Germany, DE; 4ETAS GmbH, Germany, DE Abstract We present a design space exploration demonstration applied to an industrial lane-keeping-support case study. We minimize communication, costs, weight, and the number of processing elements also satisfying hard real-time constraints for distributed embedded systems. The input system is modeled in SysML with TADL2 extensions and the SPES modeling framework from the SPES-XT project. The case study is derived from real data from the operational division of Bosch with promising results. More information ...
UB05.02	AIDA: ANALOG IC DESIGN AUTOMATION Authors: Nuno Horta1, Nuno Lourenço2, Ricardo Martins2, Ricardo Póvoa2, António Canelas2 and Pedro Ventura1 1Instituto de Telecomunicacoes, PT; 2Instituto de Telecomunicacoes / Instituto Superior Técnico, PT Abstract This demonstration presents AIDA, an analog integrated circuit (IC) design automation environment. AIDA includes two main modules, namely, AIDA-C and AIDA-L. AIDA-C is a circuit-level synthesis tool which uses state-of-the-art multi-objective multi-constrained optimization kernels, based on evolutionary computation techniques, where the robustness of the solutions is attained by considering a layout-aware approach and, also, extreme process variations by means of PVT corner analysis. The circuit's performance is measured using Spectre®, ELDO® or HSPICE® electrical simulators as evaluation engines. AIDA-L considers the device sizes and the best floorplan, obtained with AIDA-C, and generates the complete layout by placing and routing the devices, while fulfilling the technology design rules by using built-in design-rule check (DRC) and layout-versus-schematic (LVS) procedures. In order to demonstrate AIDA design environment several analog circuit structures, e.g., OTAs, LNAs, LC-Oscillators, etc., will be synthesized in a 130nm CMOS technology. AIDA-C is demonstrated for circuit-level sizing and optimization by generating a family of Pareto Optimal solutions based on user performance and functional specifications. AIDA-L is demonstrated by generating the layout of a user selected solution from AIDA-C, taking into account electrical currents information to mitigate electromigration and IR-drop effects, and also wiring symmetry for multiport multi-terminal signal nets of analog ICs. More information ...
UB05.03	KAOLIN: A MODEL-BASED EDA TOOL TO PROGRAM, REUSE OR RETARGET EMBEDDED SYSTEMS ON FPGAS. Authors: Yvan Eustache, Dominique Blouin, Mickaël Lanoé, Jean-Philippe Diguet and Philippe Coussy, Lab-STICC, Université de Bretagne-Sud, FR Abstract The demonstration presents the Kaolin EDA tool to improve and speed-up embedded systems development on FPGAs. It provides modeling abstractions to shield the user from implementation details and prevent frequent time-consuming errors. It allows you to reuse legacy projects and IPs and retarget them to other platforms with different back-end tools. The Kaolin technology is based on models of components, platforms and FPGA development tools. It allows automating platform-independent system generation including vendor tool files and scripts, verification and high-level analysis, and template-based documentation generation. Kaolin nicely fits in the development flow as a bridge between the user and low level FPGA vendor tools. User appropriation is facilitated: it requires no new language to be learnt; it allows the import of legacy codes (HDL) and the software (C/C++) to hardware migration with built-in High-Level Synthesis capabilities. Kaolin can be customized to meet domain and user-specific requirements. During the demonstration, Kaolin will be used to quickly implement a control and signal processing system deployed on a FPGA and embedded on a radio-controlled toy car. More information ...
UB05.04	SECURE CLOUD-BASED WORKFLOW-AS-A-SERVICE (WFAAS) ENVIRONMENT WITH ROLE-BASED-ACCESS-CONTROL (RBAC) FOR SOC DESIGN Authors: Sai Manoj P D1, Sai Manoj P. D.1, Hao Yu1 and Joseph Lee2 1Nanyang Technological University, SG; 2Silicon Cloud International, US Abstract The SoC design process requires multiple EDA tools, custom IP's, and technology design kit from multiple providers. The design environment needs to be secure and collaborative. These requirements can be realized by using an integrated cloud based Workflow-as-a-Service (WFaaS) design environment. We demonstrate a cloud-based design environment for a SoC design with multiple CPU cores and analog IO's. This design environment uses an innovative Role-Based-Access-Control user security model where designers interact through a web portal dashboard to perform the design workflows. More information ...
UB05.05	MOTORBRAIN: MODEL-BASED DESIGN AND VIRTUAL INTEGRATION OF AN INTELLIGENT AND SAFE ELECTRICAL POWERTRAIN Authors: Sven Rosinger, Maher Fakih and Jörg Walter, OFFIS - Institut für Informatik, DE Abstract Hardware prototypes and hardware in the loop simulations are commonly used during embedded vehicle- and motor-control unit design. This demonstrator presents a platform that is an order of magnitude cheaper than existing systems but still easy to integrate into present workflows: Within an existing model-driven design methodology, a real-time hardware simulation is performed using the Raspberry Pi single-board computer to simulate an e-motor with little development effort and in conjunction with an industrial motor control unit. More information ...
UB05.06	PHARAON: PARALLEL AND HETEROGENEOUS ARCHITECTURES FOR REAL-TIME APPLICATIONS Authors: Luciano Lavagno1, Mihai Lazarescu1, Hector Posadas2 and Eugenio Villar2 1Politecnico di Torino, IT; 2Universidad de Cantabria, ES Abstract In this demo, we will present the work-in-progress of the EU FP7 PHARAON project, started in September 2011. The first objective of the project is the development of new techniques and tools capable to assist the designer in the development of parallel embedded systems, from executable specifications to target-specific implementation and debugging on a multicore platform. This tool chain offers and implements several parallelization strategies, reflecting the functional and non-functional constraints of the system, and driving the designer into incremental parallelization and adaptation steps. The second objective of the project is to develop monitoring and control techniques in the middleware of the system capable to automatically adapt platform services to application requirements and therefore reduce power consumption transparently. The demo will cover specifically: - the software parallelization tool suite, - the parallel software modeling and code generation suite. More information ...
UB05.07	LARA: THE LARA COMPILER SUITE Authors: Joao Bispo, Pedro Pinto, Ricardo Nobre, Tiago Carvalho and Joao Cardoso, Universidade do Porto, PT Abstract LARA is an aspect-oriented programming (AOP) language which allows the description of sophisticated code instrumentation schemes, advanced mapping strategies including conditional decisions, based on hardware/software resources, and of sophisticated sequences of compiler transformations. Furthermore, LARA provides mechanisms for controlling all elements of a toolchain in a consistent and systematic way, using a unified programming interface. We present three compiler tools developed around the LARA technology, MATISSE, MANET and ReflectC. MATISSE is a compiler which 1) allows analyses and transformations on MATLAB code and 2) generates C code from the MATLAB code. MATISSE can be fully controlled through LARA aspects, which can define the type and shape of MATLAB variables, specify code insertion/removal actions, and define specialization directives and other additional information. MATISSE can output transformed MATLAB code and specialized C code. The knowledge provided by the LARA aspects allows MATISSE to generate C tailored to specific targets (e.g., use statically declared arrays to be compliant with the high-level synthesis tools such as Catapult C). MANET is a source-to-source compiler for ANSI C based on Cetus, and is controlled using LARA aspects. MANET manages to leverage the expressiveness and modularity of LARA to query and manipulate the Cetus AST, providing an easy compilation flow with main goal of code instrumentation and code transformations. LARA aspects allow for a simple selection of program elements in the code which can be analyzed or transformed, by either consulting their attributes or applying actions. Thus, MANET can be used to provide information reports based on compiler analyses, to implement sophisticated code instrumentation strategies, or to perform code optimizations and transformations. ReflectC is a C compiler based on CoSy's compiler framework. CoSy's configurability and retargetability make ReflectC particularly effective for exploration of compiler transformations and optimizations on possible architecture variations, and it is being used for hardware/software co-design and design space exploration (DSE). We will present demos of the tools and the use of LARA aspects and strategies to guide our suite of compilation tools providing: 1) C code generation from MATLAB code, according to information provided by LARA aspects; 2) Instrumentation of C code to be used for collecting specific compile and runtime information (e.g., execution time, range of values for specific variables, custom profiling); 3) User-controlled compiler optimizations targeting several architectures and DSE of sequences of compiler optimizations bearing in mind performance improvements. In addition to presenting examples for each of the tools of the LARA compilation suite, we show an execution of the complete toolchain, controlled by LARA aspects. More information ...
UB05.08	MICROTESK: RECONFIGURABLE OPEN-SOURCE FRAMEWORK FOR TEST PROGRAM GENERATION Authors: Andrei Tatarnikov, Alexander Kamkin and Artem Kotsynyak, Institute for System Programming of the Russian Academy of Sciences (ISP RAS), RU Abstract Test program generation plays a major role in functional verification of microprocessors. Due to tremendous growth in complexity of modern designs and rigid constraints on time to market, it becomes an increasingly difficult task. In spite of powerful test program generation tools available in the market, development of functional tests is still known to be the bottleneck of the microprocessor design cycle. The common problem is that it takes a significant effort to reconfigure a test program generation environment for a new microprocessor design. The model-based approach applied in the state-of-the-art tools, like Genesys-Pro (IBM Research), still does not provide enough flexibility since creating a microprocessor model is difficult and requires special knowledge and skills. MicroTESK, the open-source test program generation framework being developed at ISPRAS, offers an approach to ease customization by using light-weight formal specifications to describe the target microprocessor architecture. The approach helps reduce the effort needed to create a microprocessor model and, consequently, minimize the time required to create functional tests. In addition to gaining flexibility, the use of formal specifications also allows automated extraction of knowledge about test situations that occur in a microprocessor (coverage model), thus, facilitating creating directed tests and improving test coverage. By the present moment, a demo prototype of MicroTESK has been implemented. It uses the Sim-nML architecture description language to specify the target microprocessor architecture and provides a convenient Ruby-based language for creating test templates that serve as an abstract description of test programs to be generated. The current version of the framework focuses primarily on RISK microprocessors including ARM, MIPS and SPARK. Supported test generation methods include random, combinatorial, template-based and model-based generation. Flexible architecture of the framework allows adding support for new test generation methods. More information ...
UB05.09	LEVERAGING DYNAMIC RECONFIGURATION TO INCREASE FAULT-TOLERANCE IN FPGA-BASED SATELLITE SYSTEMS Authors: Sebastian Korf1, Dario Cozzi1, Dirk Jungewelter1, Jens Hagemeyer1, Mario Porrmann1 and Jorgen Ilstad2 1CITEC (Bielefeld University), DE; 2ESTEC (European Space Agency), DE Abstract This demonstrator shows how todays SoCs for satellite payload processing can be extended with high-speed interfaces and computing power utilizing commercial dynamically reconfigurable FPGAs. The use of these FPGAs in space environment will lead to faults due to radiation. Therefore, special methods have been developed to increase the system reliability. We will demonstrate an environment for automatic fault detection and correction in relevant applications like image and video processing. More information ...
UB05.10	RTL+: DESIGN ENVIRONMENT: WALK BEFORE YOU RUN. Authors: Somayeh Sadeghi-Kohan, Behnaz Pourmohseni, Amir Reza Nekooei, Hanieh Hashemi, Hamed Najafi Haghi and Zainalabedin Navabi, University of Tehran, IR Abstract To enable development of high level designs with hardware correspondence, synthesizability must be satisfied in a top-down manner. Thus in this work, instead of using TLM-2.0 which is not established for synthesis, we will start with a level above RT level, "RTL+". RTL+ is basically using TLM-1.0 channels and includes abstract communications and handshakings that are mainly hidden from the designer. We develop a package of SystemC channels with hardware correspondence (synthesizable HDL) for the communication between various cores (with simple interfaces) and standard buses. More information ...
12:00	End of session
12:30	Lunch Break in Exhibition Area Sandwich lunch