3.3 Addressing Process and Delay Variation in High-Level Synthesis

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Date: Tuesday 19 March 2013
Time: 14:30 - 16:00
Location / Room: Stendahl

Chair:
Lars Bauer, Karlsruhe Institute of Technology, DE

Co-Chair:
Giovanni Ansaloni, EPFL, CH

The first two papers target the problem of process variation and aging issues for high-level and instruction-set synthesis. The last paper incorporates delay variations arising from speculative adder structures in high-level synthesis.

TimeLabelPresentation Title
Authors
14:303.3.1(Best Paper Award Candidate)
PROFIT MAXIMIZATION THROUGH PROCESS VARIATION AWARE HIGH LEVEL SYNTHESIS WITH SPEED BINNING
Authors:
Zhao Mengying1, Alex Orailoglu2 and Xue Chun Jason1
1City University of Hong Kong, HK; 2University of California, US
Abstract
15:003.3.2INSTRUCTION-SET EXTENSION UNDER PROCESS VARIATION AND AGING EFFECTS
Authors:
Yuko Hara-Azumi1, Farshad Firouzi2, Saman Kiamehr2 and Mehdi Tahoori2
1Nara Institute of Science and Technology, JP; 2Karlsruhe Institute of Technology, DE
Abstract
15:303.3.3MULTISPECULATIVE ADDITIVE TREES IN HIGH-LEVEL SYNTHESIS
Authors:
Alberto A. Del Barrio1, Román Hermida1, Seda O. Memik2, José M. Mendías1 and María C. Molina1
1Complutense University of Madrid, ES; 2Northwestern University, US
Abstract
16:00IP1-11, 528MULTI-PUMPING FOR RESOURCE REDUCTION IN FPGA HIGH-LEVEL SYNTHESIS
Authors:
Andrew Canis, Jason Anderson and Stephen Brown, University of Toronto, CA
Abstract
16:01IP1-12, 380RESOURCE-CONSTRAINED HIGH-LEVEL DATAPATH OPTIMIZATION IN ASIP DESIGN
Authors:
Yuankai Chen and Hai Zhou, Northwestern University, US
Abstract
16:00End of session
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