Date: Tuesday 19 March 2013
Time: 16:00 - 16:30
Location / Room: Exhibition Hall (espace accueil)

Interactive Presentations run simulatenously during a 30-minute slot. A poster associated to the IP paper is on display throughout the afternoon. Additionally, each IP paper is briefly introduced in a one-minute presentation in a corresponding regular session, prior to the actual Interactive Presentation.

Label	Presentation Title Authors
IP1-1	AN AUTOMATED PARALLEL SIMULATION FLOW FOR HETEROGENEOUS EMBEDDED SYSTEMS Authors: Seyed Hosein Attarzadeh Niaki and Ingo Sander, KTH Royal Institute of Technology, SE Abstract
IP1-2	MUTATION ANALYSIS WITH COVERAGE DISCOUNTING Authors: Peter Lisherness, Nicole Lesperance and Kwang-Ting Cheng, University of California, Santa Barbara, US Abstract
IP1-3	SCALABLE FAULT LOCALIZATION FOR SYSTEMC TLM DESIGNS Authors: Hoang M. Le, Daniel Große and Rolf Drechsler, University of Bremen, DE Abstract
IP1-4	SMARTCAP: USER EXPERIENCE-ORIENTED POWER ADAPTATION FOR SMARTPHONE'S APPLICATION PROCESSOR Authors: Xueliang Li, Guihai Yan, Yinhe Han and Xiaowei Li, Chinese Academy of Sciences, CN Abstract
IP1-5	RUNTIME POWER ESTIMATION OF MOBILE AMOLED DISPLAYS Authors: Dongwon Kim, Wonwoo Jung and Hojung Cha, Yonsei University, KR Abstract
IP1-6	A DUAL GRAIN HIT-MISS DETECTOR FOR LARGE DIE-STACKED DRAM CACHES Authors: Michel El Nacouzi, Islam Atta, Myrto Papadopoulou, Jason Zebchuk, Natalie Enright Jerger and Andreas Moshovos, University of Toronto, CA Abstract
IP1-7	REDUCING WRITES IN PHASE-CHANGE MEMORY ENVIRONMENTS BY USING EFFICIENT CACHE REPLACEMENT POLICIES Authors: Roberto Rodriguez, Fernando Castro, Daniel Chaver, Luis Pinuel and Francisco Tirado, Complutense University, ES Abstract
IP1-8	A 100 GOPS ASP BASED BASEBAND PROCESSOR FOR WIRELESS COMMUNICATION Authors: Zhu Ziyuan, Tang Shan, Su Yongtao, Han Juan, Sun Gang and Shi Jinglin, Chinese Academy of Sciences, CN Abstract
IP1-9	HARDWARE-SOFTWARE COLLABORATIVE COMPLEXITY REDUCTION SCHEME FOR THE EMERGING HEVC INTRA ENCODER Authors: Muhammad Usman Karim Khan, Muhammad Shafique, Mateus Grellert da Silva and Jörg Henkel, Karlsruhe Institute of Technology, DE Abstract
IP1-10	AN OPEN PLATFORM FOR MIXED-CRITICALITY REAL-TIME ETHERNET Authors: Gonzalo Carvajal1 and Sebastian Fischmeister2 1Universidad de Concepcion, CL; 2University of Waterloo, CA Abstract
IP1-11	MULTI-PUMPING FOR RESOURCE REDUCTION IN FPGA HIGH-LEVEL SYNTHESIS Authors: Andrew Canis, Jason Anderson and Stephen Brown, University of Toronto, CA Abstract
IP1-12	RESOURCE-CONSTRAINED HIGH-LEVEL DATAPATH OPTIMIZATION IN ASIP DESIGN Authors: Yuankai Chen and Hai Zhou, Northwestern University, US Abstract
IP1-13	PHOENIX: REVIVING MLC BLOCKS AS SLC TO EXTEND NAND FLASH DEVICES LIFETIME Authors: Xavier Jimenez, David Novo and Paolo Ienne, École Polytechnique Fédérale de Lausanne, CH Abstract
IP1-14	NON-SPECULATIVE DOUBLE-SAMPLING TECHNIQUE TO INCREASE ENERGY-EFFICIENCY IN A HIGH-PERFORMANCE PROCESSOR Authors: Junyoung Park, Ameya Chaudhari and Jacob Abraham, The University of Texas at Austin, US Abstract
IP1-15	USER-AWARE ENERGY EFFICIENT STREAMING STRATEGY FOR SMARTPHONE BASED VIDEO PLAYBACK APPLICATIONS Authors: Hao Shen and Qinru Qiu, Syracuse University, US Abstract
IP1-16	UTILITY-AWARE DEFERRED LOAD BALANCING IN THE CLOUD DRIVEN BY DYNAMIC PRICING OF ELECTRICITY Authors: Muhammad Adnan and Rajesh Gupta, University of California, San Diego, US Abstract
IP1-17	LEAKAGE AND TEMPERATURE AWARE SERVER CONTROL FOR IMPROVING ENERGY EFFICIENCY IN DATA CENTERS Authors: Marina Zapater1, José L. Ayala2, José M. Moya3, Kalyan Vaidyanathan4, Kenny Gross4 and Ayse K. Coskun5 1CEI Campus Moncloa UCM-UPM, ES; 2Universidad Complutense de Madrid, ES; 3Universidad Politécnica de Madrid, ES; 4University of California, San Diego, US; 5Boston University, US Abstract
IP1-18	CAPTURING POST-SILICON VARIATIONS BY LAYOUT-AWARE PATH-DELAY TESTING Authors: Xiaolin Zhang, Jing Ye, Yu Hu and Xiaowei Li, Chinese Academy of Sciences, CN Abstract
IP1-19	ADAPTIVE REDUCTION OF THE FREQUENCY SEARCH SPACE FOR MULTI-VDD DIGITAL CIRCUITS Authors: Chandra Suresh1, Ender Yilmaz2, Ozgur Sinanoglu1 and Sule Ozev3 1NYU Abu Dhabi, AE; 2Freescale, US; 3Arizona State University, US Abstract