Moderators:
Christian Krieg, TU Wien, AT
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

Speaker:
Burcin Cakir, Princeton University, US

Bio:

Burcin Cakir received her B.S. degree from Electrical Engineering Department of Bilkent University, and her Ph.D. degree from Princeton University. Her research motivation is formulating models that can represent real systems accurately and express mathematical bases/frameworks for further analysis. She had experience in developing algorithms and analyses to help design secure hardware systems. She is a recipient of Francis Robbins Upton Fellowship award from Princeton University. Her work on Hardware Trojan detection received Best Paper Award at DATE Conference (2015). She also has served as a referee on various journals and conferences and gave workshop and seminar talks. Besides her work at Princeton, she also had experience in industry research with two internships at Microsoft Research (MSR) in Redmond and Cambridge Labs.

Moderators:
Christian Krieg, TU Wien, AT
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

Moderators:
Christian Krieg, TU Wien, AT
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

Moderators:
Christian Krieg, TU Wien, AT
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

Speaker:
Pramod Subramanyan, Indian Institute of Technology Kaipur, IN

Abstract:

Recent years have seen much hand-wringing about security concerns posed by malicious hardware designs. Seemingly at the other end of the spectrum are inadvertent hardware design flaws that lead to security breaches. The former concern has led to development of algorithmic reverse engineering techniques, Hardware Trojan detection algorithms and side-channel analysis algorithms -- all of which aim to algorithmically discover malicious behavior from the bottom up. The latter concern has led to the progress in top-down security verification techniques based on model checking and syntax-guided synthesis. In this talk, I will try to review some recent progress in both top-down and bottom-up analysis. I will argue that both top-down and bottom-up techniques can synergistically benefit each other.

Bio:

Pramod Subramanyan is an Assistant Professor in the Department of Computer Science and Engineering at the Indian Institute of Technology, Kanpur. He obtained his Ph.D. from Princeton University and subsequent to his Ph.D., he was a postdoctoral scholar at the University of California, Berkeley. His research interests lie at the intersection of systems security and formal methods. His current research is focused on system-building techniques that can provide verifiable guarantees of security. Pramod's research has won several awards including the Best Paper Award at the ACM Computer and Communication Security conference, the ACM SIGDA Outstanding Ph.D. Dissertation in Electronic Design Automation Award, the Best Student Paper Award at IEEE Symposium on Hardware-Oriented Security and Trust.

Moderators:
Christian Krieg, TU Wien, AT
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

Moderators:
Christian Krieg, TU Wien, AT
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE

Speaker:
David Shah, Symbiotic EDA, GB

Abstract:

The Lattice ECP5 is a family of mid-range (up to 85k logic cells) FPGAs.
Project Trellis has created open source bitstream, architecture and timing
documentation for them; in order to open up a better understanding of their
internals. This has led to the development of an end-to-end open source
Verilog to bitstream flow for these parts using Yosys for synthesis and
nextpnr for place-and-route, and opens the door to low-level
experimentation not possible within the constraints of the vendor FPGA
tools. Open source compilers such as GCC and LLVM are now widely used and
accepted in the software development community; and developing open
bitstream documentation is a first step to bringing the FPGA ecosystem to
parity with this.

This talk will describe the processes used to build this open
documentation, detail some of the interesting lessons learnt along the way,
and describe some of the possibilities that bitstream documentation bring
for development and verification - with almost everything discussed equally
applicable to FPGAs from other vendors.


Bio:
David Shah is a engineer at Symbiotic EDA and a Electronic and Information
Engineering student at Imperial College London. He entered the world of
open source FPGAs by extending Project Icestorm, the iCE40 bitstream
documentation project, to include the newer iCE40 UltraPlus FPGAs. As well
developing Project Trellis, he has been involved in the development of a
new open source FPGA place-and-route tool, nextpnr.

Moderators:
Christian Krieg, TU Wien, AT
Oliver Keszöcze, Friedrich-Alexander-Universität Erlangen-Nürnberg, DE