3D++: Unlocking the Next Generation of High-Performance and Energy-Efficient Architectures using M3D Integration
Biresh Kumar Joardar1, Aqeeb Iqbal Arka2,a, Janardhan Rao Doppa2,b and Partha Pratim Pande2,c
1Department of ECE, Duke University Durham, NC 27708, USA
bireshkumar.joardar@duke.edu
2School of EECS, Washington State University Pullman, WA 99164, U.S.A
aaqeebiqbal.arka@wsu.edu
bjana.doppa@wsu.edu
cpande@wsu.edu
ABSTRACT
Three-dimensional (3D) integration has frequently been described as a means to overcome scaling bottlenecks, and advance both “More Moore” and “More Than Moore” through the use of vertical interconnects and die/wafer stacking. Recent industry trends show the viability of 3D integration in real products. Flash memory producers have also demonstrated multiple layers of memory on top of each other. However, conventional TSV-based 3D designs cannot achieve the full-potential of vertical integration and perform sub-optimally. Monolithic 3D (M3D) is an emerging vertical integration technology that promises significant power-performance-area benefits compared to TSVs. Hence, it is important to understand the necessary design trade-offs and challenges associated with this new paradigm. In this paper, we present both the advantages and the various design challenges in M3D-enabled system design considering Processing-in-Memory (PIM) and manycore systems as suitable case-studies.
Keywords: M3D, Manycore, PIM, Thermal, Power.
