Future Computing Platform Design: A Cross-Layer Design Approach
Hsiang-Yun Cheng1,a, Chun-Feng Wu2,4, Christian Hakert3, Kuan-Hsun Chen3, Yuan-Hao Chang2, Jian-Jia Chen3,b, Chia-Lin Yang4 and Tei-Wei Kuo4,5,d
1Research Center for Information Technology Innovation, Academia Sinica, Taiwan
2Institute of Information Science, Academia Sinica, Taiwan
3Department of Computer Science, Technische Universität Dortmund, Germany
4Department of Computer Science and Information Engineering, National Taiwan University, Taiwan
5College of Engineering, City University of Hong Kong, Hong Kong
ajohnson@iis.sinica.edu.tw
bjian-jia.chen@cs.uni-dortmund.de
cyangc@csie.ntu.edu.tw
dktw@csie.ntu.edu.tw
ABSTRACT
Future computing platforms are facing a paradigm shift with the emerging resistive memory technologies. First, they offer fast memory accesses and data persistence in a single large-capacity device deployed on the memory bus, blurring the boundary between memory and storage. Second, they enable computing-in-memory for neuromorphic computing to mitigate costly data movements. Due to the non-ideality of these resistive memory devices at the moment, we envision that cross-layer design is essential to bring such a system into practice. In this paper, we showcase a few examples to demonstrate how cross-layer design can be developed to fully exploit the potential of resistive memories and accelerate its adoption for future computing platforms.
