A 93 TOPS/Watt Near-Memory Reconfigurable SAD Accelerator for HEVC/AV1/JEM Encoding
Jainaveen Sundaram1, Srivatsa Rangachar Srinivasa1, Dileep Kurian1, Indranil Chakraborty2, Sirisha Kale1, Nilesh Jain1, Tanay Karnik1, Ravi Iyer1 and Anuradha Srinivasan1
1Intel Labs, 2111 NE 25th Ave, Hillsboro OR 97124 USA
2Purdue University, West Lafayette, IN 479006 USA
ABSTRACT
Motion Estimation (ME) is a major bottleneck of a Video encoding pipeline. This paper presents a low power near memory Sum of Absolute Difference (SAD) accelerator for ME. The accelerator is composed of 64 modular SAD Processing Elements (PEs) on a Reconfigurable fabric, offering maximal parallelism to support traditional and futuristic Rate-Distortion-Optimization (RDO) schemes consistent with HEVC/AV1/JEM. The accelerator offers up-to 55% speedup over State-of-art accelerators and a 7x speedup when compared to a 12 core Intel Xeon E5 processor. Our solution achieves 93 TOPS/Watt running at 500MHz frequency, capable of processing real-time 4K 30fps video. Synthesized in 22nm process, the accelerator occupies 0.08mm2 and consumes 5.46mW dynamic power.
Keywords: Near Memory Compute, Motion Estimation, Accelerator.
