A 3-D LUT Design for Transient Error Detection Via Inter-Tier In-Silicon Radiation Sensor
Sarah Azimia, Corrado De Siob and Luca Sterponec
Department of Control and Computer Engineering Politecnico di Torino Torino, Italy
ABSTRACT
Three-dimensional Integrated Circuits (3-D ICs) have gained much attention as a promising approach to increase IC performance due to their several advantages in terms of integration density, power dissipation, and achievable clock frequencies. However, achieving a 3-D ICs resilient to soft errors resulting from radiation effects is a challenging problem. Traditional Radiation-Hardened-by-Design (RHBD) techniques are costly in terms of area, power, and performance overheads. In this work, we propose a new 3-D LUT design integrating error detection capabilities. The LUT has been designed on a two tiers IC model improving radiation resiliency by selective upsizing of sensitive transistors. Besides, an in-silicon radiation sensor adopting inverters chain has been implemented within the free volume of the 3-D structure. The proposed design shows a 37% reduction in sensitivity to SETs and an effective error detection rate of 83% without introducing any area overhead.
Keywords: 3D IC, Single Event Transient, Gate Sizing, In- Silicon Radiation Sensor.
