Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors
Adrià Armejach1,2, Bine Brank3, Jordi Cortina5, François Dolique5, Timothy Hayes6, Nam Ho3, Pierre-Axel Lagadec7, Romain Lemaire5, Guillem López-Paradís1,2, Laurent Marliac7, Miquel Moretó1,2, Pedro Marcuello4, Dirk Pleiter3, Xubin Tan4 and Said Derradji7
1Barcelona Supercomputing Center
2Universitat Politècnica de Catalunya
3Forschungszentrum Juelich, Juelich Supercomputing Centre
4Semidynamics Technology Services, SL
5Univ. Grenoble Alpes, CEA, List, F-38000 Grenoble, France
6Arm
7Atos
ABSTRACT
AThe Mont-Blanc 2020 (MB2020) project has triggered the development of the next generation industrial processor for Big Data and High Performance Computing (HPC). MB2020 is paving the way to the future low-power European processor for exascale, defining the System-on-Chip (SoC) architecture and implementing new critical building blocks to be integrated in such an SoC. In this paper, we first present an overview of the MB2020 project, then we describe our experimental infrastructure, the requirements of relevant applications, and the IP blocks developed in the project. Finally, we present our emulation-based final demonstrator and explain how it integrates within our first generation of HPC processors.
