RISC-V for Real-time MCUs - Software Optimization and Microarchitectural Gap Analysis
Robert Balasa and Luca Beninib
Integrated Systems Laboratory, ETH Zurich, Switzerland
abalasr@iis.ee.ethz.ch
blbenini@iis.ee.ethz.ch
ABSTRACT
Processors using the RISC-V ISA are finding increasing real use in IoT and embedded systems in the MCU segment. However, many real-life use cases in this segment have realtime constraints. In this paper we analyze the current state of real-time support for RISC-V with respect to the ISA, available hardware and software stack focusing on the RV32IMC subset of the ISA. As a reference point, we use the CV32E40P, an opensource industrially supported RV32IMFC core and FreeRTOS, a popular open-source real-time operating system, to do a baseline characterization. We perform a series of software optimizations on the vanilla RISC-V FreeRTOS port where we also explore and make use of ISA and micro-architectural features, improving the context switch time by 25% and the interrupt latency by 33% in the average and 20% in the worst-case run on a CV32E40P when evaluated on a power control unit firmware and synthetic benchmarks. This improved version serves then in a comparison against the ARM Cortex-M series, which in turn allows us to highlight gaps and challenges to be tackled in the RISC-V ISA as well as in the hardware/software ecosystem to achieve competitive maturity.
Keywords: RISC-V, FreeRTOS, Real-Time, Open-Source.
